Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 12 Bit, 14 Bit NFBGA 135

AFE5808

www.ti.com

SLOS688C –SEPTEMBER 2010–REVISED APRIL 2012

Fully Integrated, 8-Channel Ultrasound Analog Front End with Passive CW Mixer,

0.75nV/rtHz, 14/12-Bit, 65MSPS, 153mW/CH

Check for Samples: AFE5808

FEATURES

APPLICATIONS

• 8-Channel Complete Analog Front-End • Medical Ultrasound Imaging

– LNA, VCAT, PGA, LPF, ADC, and CW Mixer • Nondestructive Evaluation Equipments

DESCRIPTION

• Programmable Gain Low-Noise Amplifier

The AFE5808 is a highly integrated Analog Front-End

(LNA)

(AFE) solution specifically designed for ultrasound

– 24/18/12 dB Gain

systems in which high performance and small size

– 0.25/0.5/1 V

Linear Input Range

are required. The AFE5808 integrates a complete

time-gain-control (TGC) imaging path and a

– 0.63/0.7/0.9 nV/rtHz Input Referred Noise

continuous wave Doppler (CWD) path. It also enables

– Programmable Active Termination

users to select one of various power/noise

• 40 dB Low Noise Voltage Controlled

combinations to optimize system performance.

Attenuator (VCAT)

Therefore, the AFE5808 is a suitable ultrasound

analog front end solution not only for high-end

• 24/30 dB Programmable Gain Amplifier (PGA)

systems, but also for portable ones.

• 3

Order Linear Phase Low-Pass Filter (LPF)

The AFE5808 contains eight channels of voltage

– 10, 15, 20, 30 MHz

controlled amplifier (VCA), 14/12-bit Analog-to-Digital

• 14-bit Analog to Digital Converter (ADC)

Converter (ADC), and CW mixer. The VCA includes

– 77 dBFS SNR at 65 MSPS

Low noise Amplifier(LNA), Voltage controlled

Attenuator(VCAT), Programmable Gain

– LVDS Outputs

Amplifier(PGA), and Low-Pass Filter (LPF). The LNA

• Noise/Power Optimizations (Full Chain)

gain is programmable to support 250 mV

to 1 V

– 153 mW/CH at 0.75 nV/rtHz, 65 MSPS

input signals. Programmable active termination is

– 98 mW/CH at 1.1 nV/rtHz, 40 MSPS

also supported by the LNA. The ultra-low noise VCAT

provides an attenuation control range of 40dB and

– 80 mW/CH at CW Mode

improves overall low gain SNR which benefits

• Excellent Device-to-Device Gain Matching

harmonic imaging and near field imaging. The PGA

– ±0.5 dB(typical) and ±0.9 dB(max)

provides gain options of 24 dB and 30 dB. Before the

ADC, a LPF can be configured as 10 MHz, 15 MHz,

• Low Harmonic Distortion

20 MHz or 30 MHz to support ultrasound applications

• Fast and Consistent Overload Recovery

with different frequencies. The high-performance 14

• Passive Mixer for Continuous Wave

bit/65 MSPS ADC in the AFE5808 achieves 77 dBFS

Doppler(CWD)

SNR. It ensures excellent SNR at low chain gain. The

ADC’s LVDS outputs enable flexible system

– Low Close-in Phase Noise –156 dBc/Hz at 1

integration desired for miniaturized systems.

KHz off 2.5 MHz Carrier

– Phase Resolution of 1/16λ

– Support 16X, 8X, 4X and 1X CW Clocks

– 12dB Suppression on 3

and 5

Harmonics

– Flexible Input Clocks

• Small Package: 15 mm x 9 mm, 135-BGA

NOTE

AFE5808A is an enhanced version of AFE5808 and it is recommended for new designs.

Compared to AFE5808, it expands the cut-off frequency range of the digital high pass

filter; increases the handling capability of extreme overload signals; lowers the correlated

noise significantly when high impedance source appears.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (68 pages)

PAGE 1
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 Fully Integrated, 8-Channel Ultrasound Analog Front End with Passive CW Mixer, 0.75nV/rtHz, 14/12-Bit, 65MSPS, 153mW/CH Check for Samples: AFE5808 FEATURES APPLICATIONS • • • 1 • • • • • • • • • • • 8-Channel Complete Analog Front-End – LNA, VCAT, PGA, LPF, ADC, and CW Mixer Programmable Gain Low-Noise Amplifier (LNA) – 24/18/12 dB Gain – 0.25/0.5/1 VPP Linear Input Range – 0.63/0.7/0.
PAGE 2
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Supply voltage range UNIT MAX MIN AVDD –0.3 3.9 V AVDD_ADC –0.3 2.2 V AVDD_5V –0.3 6 V DVDD –0.3 2.2 V Voltage between AVSS and LVSS –0.3 0.3 V Voltage at analog inputs and digital inputs –0.3 min [3.6,AVDD+0.
PAGE 4
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.
PAGE 5
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 PIN FUNCTIONS (continued) PIN DESCRIPTION NO. NAME E1 CW_IP_AMPINP Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be connected between CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive output when PGA test mode is enabled. Can be floated if not used. F1 CW_IP_OUTM Negative differential output for the In-phase summing amplifier.
PAGE 6
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.
PAGE 7
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.
PAGE 8
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.
PAGE 9
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, AC-coupled with 0.
PAGE 10
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com DIGITAL CHARACTERISTICS Typical values are at +25°C, AVDD = 3.3V, AVDD_5 = 5V and AVDD_ADC = 1.8V, DVDD = 1.8V unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = 0°C to TMAX = +85°C,. PARAMETER CONDITION MIN TYP MAX UNITS (1) DIGITAL INPUTS/OUTPUTS VIH Logic high input voltage 2 3.3 VIL Logic low input voltage 0 0.
PAGE 11
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, ac-coupled with 0.1µF caps at INP and 15nF caps at INM, No active termination, VCNTL = 0V, FIN = 5MHz, LNA = 18dB, PGA = 24dB, 14Bit, sample rate = 65MSPS, LPF Filter = 15MHz, low noise mode, VOUT = -1dBFS, 500Ω CW feedback resistor, CMOS 16X clock, ADC is configured in internal reference mode, Single-ended VCNTL mode, VCNTLM = GND.
PAGE 12
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 60 180 160 Number of Occurrences Number of Occurrences 50 140 120 100 80 60 40 40 30 20 10 20 0 0 −0.9−0.8−0.7−0.6−0.5−0.4−0.3−0.2−0.1 0 Gain Error (dB) 0.1 0.2 0.3 0.4 −50 Figure 6. Gain Matching Histogram, VCNTL = 0.9V (936 channels) −40 −30 −20 −10 0 10 ADC Output 20 30 40 50 Figure 7.
PAGE 13
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) LNA INPUT HPF CHARACTERISTICS 5 10MHz 15MHz 20MHz 30MHz 0 0 −3 −6 Amplitude (dB) Amplitude (dB) −5 3 −10 −15 −20 −9 −12 −15 −18 −21 −25 −30 01 00 11 10 −24 −27 0 10 20 30 40 50 60 −30 Frequency (MHz) 10 100 500 Frequency (KHz) Figure 12. Low-Pass Filter Response Figure 13. LNA High-Pass Filter Response vs.
PAGE 14
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Hz) 40.0 3.5 LNA 12 dB LNA 18 dB LNA 24 dB Input reffered noise (nV Hz) 50.0 Input reffered noise (nV 60.0 30.0 20.0 10.0 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Vcntl (V) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 Figure 18. IRN, PGA = 24dB and Low Noise Mode Hz) Input reffered noise (nV Hz) Input reffered noise (nV 40.0 30.0 20.0 10.0 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.
PAGE 15
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) 190.0 170.0 300.0 280.0 260.0 240.0 220.0 200.0 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Vcntl (V) Hz) LNA 12 dB LNA 18 dB LNA 24 dB Output reffered noise (nV Output reffered noise (nV Hz) 220.0 210.0 150.0 130.0 110.0 90.0 70.0 50.0 30.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Vcntl (V) 1.2 LNA 12 dB LNA 18 dB LNA 24 dB 1.1 1.0 Hz) 340.
PAGE 16
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 75.0 73.0 Low noise Low power mode 71.0 69.0 SNR (dBFS) SNR (dBFS) 70.0 65.0 60.0 67.0 65.0 63.0 61.0 59.0 24 dB PGA gain 30 dB PGA gain 55.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Vcntl (V) 57.0 0 Figure 30. SNR, LNA = 18dB and Low Power Mode 9.0 8.0 6.0 5.0 4.0 3.0 7.0 4.0 3.0 2.0 1.0 100.0 150.0 200.0 250.0 300.0 350.0 0.0 50.0 400.
PAGE 17
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) 4.0 −50 Low noise Low power Medium power Low noise Medium power Low power −52 HD2 (dBc) Noise Figure (dB) −54 3.0 2.0 −56 −58 −60 −62 −64 1.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 −66 400.0 1 2 3 Source Impedence (Ω) 4 5 6 7 8 9 10 Frequency (MHz) Figure 36. Noise Figure vs. Power Modes without Termination Figure 37. HD2 vs.
PAGE 18
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) −40 −40 Low noise Medium power Low power −50 HD2 (dBc) HD3 (dBc) −50 −60 −70 −60 −70 −80 −90 Low noise Medium Power Low power −80 12 18 24 30 36 −90 42 18 24 30 Gain (dB) −50.0 Fin1=2MHz, Fin2=2.01MHz Fin1=5MHz, Fin2=5.01MHz Low noise Medium power Low power −54.0 IMD3 (dBFS) −50 −60 −70 −58.0 −62.0 −66.0 −80 18 21 24 27 30 33 36 39 42 45 −70.0 14.0 48 18.
PAGE 19
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) PSMR vs SUPPLY FREQUENCY 3V PSRR vs SUPPLY FREQUENCY −20 −55 Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 PSRR wrt supply tone (dB) PSMR (dBc) −60 Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 −30 −65 −70 −75 −40 −50 −60 −70 −80 5 10 100 −90 1000 2000 5 10 100 Supply frequency (kHz) Supply frequency (kHz) Figure 48.
PAGE 20
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.2 10000.0 1.0 8000.0 0.8 Positive overload Negative overload Average 6000.0 0.6 4000.0 Output Code Input (V) 0.4 0.2 0.0 −0.2 −0.4 2000.0 0.0 −2000.0 −4000.0 −0.6 −6000.0 −0.8 −8000.0 −1.0 −1.2 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 Time (µs) −10000.0 0.0 Figure 54. Pulse Inversion Asymmetrical Negative Input 4.0 5.0 6.
PAGE 21
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 TIMING CHARACTERISTICS (1) Typical values are at 25°C, AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, Differential clock, CLOAD = 5pF, RLOAD = 100Ω, 14Bit, sample rate = 65MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range TMIN = 0°C to TMAX = 85°C with AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.
PAGE 22
12-Bit 6x serialization mode 22 Output Data CHnOUT Data rate = 14 x fCLKIN Bit Clock DCLK Freq = 7 x fCLKIN Frame Clock FCLK Freq = fCLKIN Input Clock CLKIN Freq = fCLKIN Input Signal D0 D13 D12 D1 (D12) (D13) (D0) (D1) D11 (D2) Submit Documentation Feedback Product Folder Links: AFE5808 D13 (D0) D10 D9 (D3) (D4) D6 D5 (D7) (D8) Bit Clock Output Data Pair Data bit in LSB First mode D13 D12 (D0) (D1) CHi out tsu DCLKM DCLKP Cd clock cycles latency D4 D3 D2 D1 D0 (D9) (D10) (D11) (D12) (
PAGE 23
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 LVDS Output Interface Description AFE5808 has LVDS output interface which supports multiple output formats. The ADC resolutions can be configured as 12bit or 14bit as shown in the LVDS timing diagrams Figure 58. The ADCs in the AFE5808 are running at 14bit; 2 LSBs are removed when 12-bit output is selected; and two 0s are added at LSBs when 16-bit output is selected.
PAGE 24
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com SPI Timing Characteristics Minimum values across full temperature range TMIN = 0°C to TMAX = 85°C, AVDD_5V = 5V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.
PAGE 25
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 t1 AVDD AVDD_5V AVDD_ADC t2 DVDD t3 t4 t7 t5 RESET t6 Device Ready for Serial Register Write SEN Start of Clock Device Ready for Data Conversion CLKP_ADC t8 10µs < t1 < 50ms, 10µs < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100µs. The AVDDx and DVDD power-on sequence does not matter as long as –10 ms < t3 < 10 ms. Similar considerations apply while shutting down the device. Figure 61.
PAGE 26
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com Register Map A reset process is required at the AFE5808 initialization stage. Initialization can be done in one of two ways: 1. Through a hardware reset, by applying a positive pulse in the RESET pin 2. Through a software reset, using the serial interface, by setting the SOFTWARE RESET bit to high.
PAGE 27
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 Table 2. ADC Register Map (continued) ADDRESS (DEC) ADDRESS (HEX) Default Value 3[12] 0x3[12] 0 DIGITAL_GAIN_ENABLE 0: No digital gain; 1: Digital gain Enabled 3[14:13] 0x3[14:13] 0 SERIALIZED_DATA_RATE Serialization factor 00: 14x 01: 16x 10: reserved 11: 12x when 4[1]=1.
PAGE 28
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com AFE5808 ADC Register/Digital Processing Description The ADC in the AFE5808 has extensive digital processing functionalities which can be used to enhance ultrasound system performance. The digital processing blocks are arranged as in Figure 62. ADC Output 12/14b Channel Average Default=No Digital Gain Default=0 Digital HPF Default = No 12/14b Final Digital Output Digital Offset Default=No Figure 62.
PAGE 29
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 Table 3. Digital HPF –1dB Corner Frequency vs. K and Fs k 40 MSPS 50 MSPS 65 MSPS 2 2780 KHz 3480 KHz 4520 KHz 3 1490 KHz 1860 KHz 2420 KHz 4 770 KHz 960 KHz 1250 KHz LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11] The low-frequency noise suppression mode is especially useful in applications where good noise performance is desired in the frequency band of 0MHz to 1MHz (around dc).
PAGE 30
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com TEST_PATTERN_MODES: Address: 2[15:13] The AFE5808 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal ADC data output. The device may also be made to output 6 preset patterns: 1. Ramp: Setting Register 2[15:13]=111causes all the channels to output a repeating full-scale ramp pattern. The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle.
PAGE 31
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 VCA Register Map Table 4. VCA Register Map ADDRESS ADDRESS Default (DEC) (HEX) Value FUNCTION DESCRIPTION 51[0] 0x33[0] 0 RESERVED 0 51[3:1] 0x33[3:1] 0 LPF_PROGRAMMABILITY 000: 010: 011: 100: 51[4] 0x33[4] 0 PGA_INTEGRATOR_DISABLE (PGA_HPF_DISABLE) 0: Enable 1: Disables offset integrator for PGA.
PAGE 32
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com Table 4. VCA Register Map (continued) ADDRESS ADDRESS Default (DEC) (HEX) Value FUNCTION DESCRIPTION 53[7:0] 0x35[7:0] 0 PDN_CH<7:0> 0: Normal operation; 1: Powers down corresponding channels. Bit7→CH8, Bit6→CH7…Bit0→CH1.
PAGE 33
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 Table 4.
PAGE 34
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com Table 6. Register 52[4:0] vs LNA Input Impedances 52[4:0]/0x34[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 LNA:12dB High Z 150 Ω 300 Ω 100 Ω 600 Ω 120 Ω 200 Ω 86 Ω LNA:18dB High Z 90 Ω 180 Ω 60 Ω 360 Ω 72 Ω 120 Ω 51 Ω LNA:24dB High Z 50 Ω 100 Ω 33 Ω 200 Ω 40 Ω 66.
PAGE 35
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 Programmable Gain for CW Summing Amplifier Different gain can be configured for the CW summing amplifier through the register 54[4:0]. By enabling and disabling the feedback resistors between the summing amplifier inputs and outputs, the gain is adjustable accordingly to maximize the dynamic range of CW path. Table 7 describes the relationship between the summing amplifier gain and 54[4:0] settings. Table 7.
PAGE 36
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com THEORY OF OPERATION AFE5808 OVERVIEW The AFE5808 is a highly integrated Analog Front-End (AFE) solution specifically designed for ultrasound systems in which high performance and small size are required. The AFE5808 integrates a complete time-gaincontrol (TGC) imaging path and a continuous wave Doppler (CWD) path. It also enables users to select one of various power/noise combinations to optimize system performance.
PAGE 37
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 filter. The effective corner frequency is determined by the capacitor CBYPASS connected at INM. With larger capacitors, the corner frequency is lower. For stable operation at the highest HP filer cut-off frequency, a ≥15 nF capacitor can be selected. This corner frequency scales almost linearly with the value of the CBYPASS.
PAGE 38
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com Additionally, a digitally controlled TGC mode is implemented to achieve better phase-noise performance in the AFE5808. The attenuator can be controlled digitally instead of the analog control voltage VCNTL. This mode can be set by the register bit 59[7]. The variable voltage divider is implemented as a fixed series resistance and FET as the shunt resistance. Each FET can be turned ON by connecting the switches SW1-7.
PAGE 39
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 PROGRAMMABLE GAIN AMPLIFIER (PGA) After the voltage controlled attenuator, a programmable gain amplifier can be configured as 24dB or 30dB with a constant input referred noise of 1.75nV/rtHz. The PGA structure consists of a differential voltage-to-current converter with programmable gain, clamping circuits, a transimpedance amplifier with a programmable low-pass filter, and a DC offset correction circuit.
PAGE 40
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com CONTINUOUS-WAVE (CW) BEAMFORMER Continuous-wave Doppler is a key function in mid-end to high-end ultrasound systems. Compared to the TGC mode, the CW path needs to handle high dynamic range along with strict phase noise performance. CW beamforming is often implemented in analog domain due to the mentioned strict requirements.
PAGE 41
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 ACT1 500Ω IN1 INPUT1 INM1 Mixer Clock 1 LNA1 Cext 500Ω ACT2 500Ω IN2 INPUT2 INM2 Mixer Clock 2 CW_AMPINM 10Ω 10Ω LNA2 500Ω Rint/Rext CW_OUTP I/V Sum Amp Rint/Rext CW _AMPINP CW_OUTM Cext CW I or Q CHANNEL Structure ACT8 500Ω IN8 INPUT8 INM8 Mixer Clock 8 LNA8 500Ω Note: the 10Ω resistors at CW_AMPINM/P are due to internal IC routing and can create slight attenuation. Figure 69.
PAGE 42
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com From the above equations, the 3rd and 5th order harmonics from the LO can interface with the 3rd and 5th order harmonic signals in the Vi(t); or the noise around the 3rd and 5th order harmonics in the Vi(t). Therefore the mixer’s performance is degraded. In order to eliminate this side effect due to the square-wave demodulation, a proprietary harmonic suppression circuit is implemented in the AFE5808.
PAGE 43
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 Fin 16X Clock INV D Q Fin 1X Clock Fin 1X Clock 16 Phase Generator 1X Clock Phase 0º 1X Clock Phase 22.5º SPI 1X Clock Phase 292.5º 1X Clock Phase 315º 1X Clock Phase 337.5º 16-to-8 Cross Point Switch Mixer 1 1X Clock Mixer 2 1X Clock Mixer 3 1X Clock Mixer 6 1X Clock Mixer 7 1X Clock Mixer 8 1X Clock Figure 71. Fin 1X Clock Fin 16X Clock 1X Clock Phase 0° 1X Clock Phase 22.
PAGE 44
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com INV 4X/8X Clock I/Q CLK Generator D Q 1X Clock LNA2~8 In-phase CLK Summed In-Phase Quadrature CLK I/V Weight Weight LNA1 I/V Weight Summed Quadrature Weight Figure 73. 8 X ƒcw and 4 X ƒcw Block Diagram Fin 1X Clock Fin 4X Clock 1X Clock Phase 0° 1X Clock Phase 90° Quadrature clocks Figure 74.
PAGE 45
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 EQUIVALENT CIRCUITS CM CM (a) INP (b) INM (c) ACT S0492-01 Figure 76. Equivalent Circuits of LNA inputs S0493-01 Figure 77. Equivalent Circuits of VCNTLP/M VCM 5 kΩ 5 kΩ CLKP CLKM (a) CW 1X and 16X Clocks (b) ADC Input Clocks S0494-01 Figure 78.
PAGE 46
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com (a) CW_OUTP/M (b) CW_AMPINP/M S0495-01 Figure 79. Equivalent Circuits of CW Summing Amplifier Inputs and Outputs + – Low +Vdiff High AFE5808 OUTP + – –Vdiff + – High Vcommon Low External 100-W Load Rout OUTM Switch impedance is nominally 50 W (±10%) S0496-01 Figure 80.
PAGE 47
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 APPLICATION INFORMATION 0.1μF AVSS IN CH1 IN CH2 IN CH3 IN CH4 IN CH5 IN CH6 IN CH7 IN CH8 1.4V 0.1μF N*0.1μF AVSS 1.8VD DVDD AVDD N*0.1μF AVSS 10μF N*0.1μF DVSS D1P 0.1μF IN1P D1M 0.1μF 15nF IN1M D2P 0.1μF 1μF ACT2 D2M 0.1μF IN2P D3P 15nF IN2M D3M 1μF ACT3 D4P 0.1μF CLKP_1X 0.1μF CLKM_1X 0.1μF IN3P D4M 15nF IN3M D5P 1μF ACT4 D5M 0.1μF IN4P D6P 15nF IN4M D6M 1μF ACT5 0.
PAGE 48
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com A typical application circuit diagram is listed above. The configuration for each block is discussed below. LNA CONFIGURATION LNA Input Coupling and Decoupling The LNA closed-loop architecture is internally compensated for maximum stability without the need of external compensation components. The LNA inputs are biased at 2.4V and AC coupling is required. A typical input configuration is shown in Figure 82.
PAGE 49
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 CM_BYP and VHIGH pins, which generate internal reference voltages, need to be decoupled with ≥1µF capacitors. Bigger bypassing capacitors (>2.2µF) may be beneficial if low frequency noise exists in system. LNA Noise Contribution The noise spec is critical for LNA and it determines the dynamic range of entire system. The LNA of the AFE5808 achieves low power and an exceptionally low-noise voltage of 0.63nV/√Hz, and a low current noise of 2.
PAGE 50
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com Under the no termination configuration, the input impedance of the AFE5808 is about 6KΩ (8K//20pF) at 1 MHz. Passive termination requires external termination resistor Rt, which contributes to additional thermal noise. The LNA supports active termination with programmable values, as shown in Figure 84 . 450Ω 900Ω 1800Ω ACTx 3600Ω 4500Ω INPx Input INMx LNAx AFE S0500-01 Figure 84.
PAGE 51
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 LNA Gain Switch Response The LNA gain is programmable through SPI. The gain switching time depends on the SPI speed as well as the LNA gain response time. During the switching, glitches might occur and they can appear as artifacts in images. LNA gain switching in a single imaging line may not be preferred, although digital signal processing might be used here for glitch suppression.
PAGE 52
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com As discussed in the theory of operation, the attenuator architecture uses seven attenuator segments that are equally spaced in order to approximate the linear-in-dB gain-control slope. This approximation results in a monotonic slope; the gain ripple is typically less than ±0.5dB. The control voltage input (VCNTLM/P pins) represents a high-impedance input.
PAGE 53
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 CW OPERATION CW Summing Amplifier In order to simplify CW system design, a summing amplifier is implemented in the AFE5808 to sum and convert 8-channel mixer current outputs to a differential voltage output. Low noise and low power are achieved in the summing amplifier while maintaining the full dynamic range required in CW operation.
PAGE 54
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com CEXT REXT 250Ω 250Ω RINT 500Ω 1000Ω 2000Ω CW_AMPINP CW_AMPINM CW_OUTM I/V Sum Amp CW_OUTP 250Ω 250Ω 500Ω RINT 1000Ω 2000Ω REXT CEXT S0501-01 Figure 86. CW Summing Amplifier Block Diagram Multiple AFE5808s are usually utilized in parallel to expand CW beamformer channel count. These AFE5808s’ CW outputs can be summed and filtered externally further to achieve desired gain and filter response.
PAGE 55
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 AFE No.4 AFE No.3 AFE No.2 ACT1 500 Ω INP1 INPUT1 INM1 AFE No.1 Mixer 1 Clock LNA1 500 Ω ACT2 500 Ω INP2 INPUT2 INM2 Ext Sum Amp Cext Mixer 2 Clock Rint/Rext CW_AMPINP CW_AMPINM LNA2 I/V Sum Amp CW_OUTM CW_OUTP Rint/Rext 500 Ω CAC RSUM Cext CW I or Q CHANNEL Structure ACT8 500 Ω INP8 INPUT8 INM8 Mixer 8 Clock LNA8 500 Ω S0502-01 Figure 87.
PAGE 56
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com 3.3 V 130 Ω 83 Ω CDCM7005 CDCE7010 3.3 V 0.1 μF AFE CLOCKs 0.1 μF 130 Ω LVPECL (a) LVPECL Configuration 100 Ω CDCE72010 0.1 μF 0.1 μF AFE CLOCKs LVDS (b) LVDS Configuration 0.1μF 0.1μF CLOCK SOURCE 0.1μF AFE CLOCKs 50 Ω 0.1μF (c) Transformer Based Configuration CMOS CLK Driver AFE CMOS CLK CMOS (d) CMOS Configuration S0503-01 Figure 88.
PAGE 57
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 In the 16/8/4×fcw operations modes, low phase noise clock is required for 16/8/4×ƒcw clocks (i.e. CLKP_16X/ CLKM_16X pins) in order to maintain good CW phase noise performance. The 1×ƒcw clock (i.e. CLKP_1X/ CLKM_1X pins) is only used to synchronize the multiple AFE5808 chips and is not used for demodulation. Thus 1×fcw clock’s phase noise is not a concern.
PAGE 58
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com FPGA Clock/ Noisy Clock n×16×CW Freq TI Jitter Cleaner CDCE72010/ CDCM 7005 16X CW CLK 1X CW CLK CDCLVP1208 1-to-8 CLK Buffer CDCLVP1208 1-to-8 CLK Buffer AFE AFE AFE AFE 8 Synchronized 1X CW CLKs AFE AFE AFE AFE 8 Synchronized 16 X CW CLKs B0436-01 Figure 89.
PAGE 59
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 FPGA Clock/ Noisy Clock n×(20~65)MHz TI Jitter Cleaner CDCE72010/ CDCM7005 20~65 MHz ADC CLK CDCLVP1208 1-to-8 CLK Buffer CDCE72010 has 10 outputs thus the buffer may not be needed for 64CH systems AFE AFE AFE AFE AFE AFE AFE AFE 8 Synchronized ADC CLKs B0437-01 Figure 90.
PAGE 60
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com POWER MANAGEMENT Power/Performance Optimization The AFE5808 has options to adjust power consumption and meet different noise performances. This feature would be useful for portable systems operated by batteries when low power is more desired. See the characteristics information listed in the table of electrical characteristics as well as the typical characteristic plots.
PAGE 61
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 Complete Power-Down Mode To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5808 can be placed into a complete power-down mode. This mode is controlled through the registers ADC_COMPLETE_PDN, VCA_COMPLETE_PDN or PDN_GLOBAL pin. In the complete power-down mode, all circuits including reference circuits within the AFE5808 are powered down; and the capacitors connected to the AFE5808 are discharged.
PAGE 62
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com PGA_P Cext 5K ACT 500 Ω INP INPUT INM Mixer Clock Rint/Rext CW_AMPINP CW_AMPINM LNA 500 Ω CW_OUTM I/V Sum Amp Rint/Rext CW_OUTP 5K Cext PGA_M S0504-01 Figure 91. AFE5808 PGA Test Mode POWER SUPPLY, GROUNDING AND BYPASSING In a mixed-signal system design, power supply and grounding design plays a significant role. The AFE5808 distinguishes between two different grounds: AVSS(Analog Ground) and DVSS(digital ground).
PAGE 63
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 High-speed mixed signal devices are sensitive to various types of noise coupling. One primary source of noise is the switching noise from the serializer and the output buffer/drivers. For the AFE5808, care has been taken to ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount.
PAGE 64
AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com REVISION HISTORY Changes from Original (September 2010) to Revision A • Page Changed From: Product Preview To: Production Data ........................................................................................................ 1 Changes from Revision A (December 2010) to Revision B Page • Added text to the pin Description for B9~ B2 (ACT1...ACT8) ....................................................................................
PAGE 65
AFE5808 www.ti.com SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 Changes from Revision B (August 2011) to Revision C Page • Changed the data sheet title From: 8-Channel Ultrasound Analog Front End for Ultrasound... To: 8-Channel Ultrasound Analog Front End ............................................................................................................................................... 1 • Added the AFE5808A Note to the Description text ...................................................
PAGE 66
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) AFE5808ZCF ACTIVE Package Type Package Pins Package Drawing Qty NFBGA ZCF 135 160 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) SNAGCU Level-3-260C-168 HR (4) 0 to 70 AFE5808 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 67
PAGE 68
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.