Datasheet

FPGA Clock/
NoisyClock
n×16×CWFreq
TIJitterCleaner
CDCE72010/
CDCM7005
CDCLVP1208
1-to-8
CLKBuffer
CDCLVP1208
1-to-8
CLKBuffer
16XCW
CLK
1XCW
CLK
8 Synchronized
16XCWCLKs
8 Synchronized
1XCWCLKs
AFE AFE AFE AFE AFE AFE AFE AFE
B0436-01
AFE5808A
www.ti.com SLOS729B –OCTOBER 2011–REVISED APRIL 2012
In the 16/8/4×fcw operations modes, low phase noise clock is required for 16/8/4׃
cw
clocks (i.e. CLKP_16X/
CLKM_16X pins) in order to maintain good CW phase noise performance. The 1׃
cw
clock (i.e. CLKP_1X/
CLKM_1X pins) is only used to synchronize the multiple AFE5808A chips and is not used for demodulation. Thus
1×fcw clock’s phase noise is not a concern. However, in the 1×fcw operation mode, low phase noise clocks are
required for both CLKP_16X/ CLKM_16X and CLKP_1X/ CLKM_1X pins since both of them are used for mixer
demodulation. In general, higher slew rate clock has lower phase noise; thus clocks with high amplitude and fast
slew rate are preferred in CW operation. In the CMOS clock mode, 5V CMOS clock can achieve the highest slew
rate.
Clock phase noise can be improved by a divider as long as the divider’s phase noise is lower than the target
phase noise. The phase noise of a divided clock can be improved approximately by a factor of 20logN dB where
N is the dividing factor of 16, 8, or 4. If the target phase noise of mixer LO clock 1×fcw is 160 dBc/Hz at 1KHz off
carrier, the 16×fcw clock phase noise should be better than 160 - 20log16 = 136 dBc/Hz. TI’s jitter cleaners
CDCM7005 and CDCE72010 exceed this requirement and can be selected for the AFE5808A. In the 4X/1X
modes, higher quality input clocks are expected to achieve the same performance since N is smaller. Thus the
16X mode is a preferred mode since it reduces the phase noise requirement for system clock design. In addition,
the phase delay accuracy is specified by the internal clock divider and distribution circuit. Note in the 16X
operation mode, the CW operation range is limited to 8 MHz due to the 16X CLK. The maximum clock frequency
for the 16X CLK is 128 MHz. In the 8X, 4X, and 1X modes, higher CW signal frequencies up to 15 MHz can be
supported with small degradation in performance, e.g. the phase noise is degraded by 9 dB at 15 MHz,
compared to 2 MHz.
As the channel number in a system increases, clock distribution becomes more complex. It is not preferred to
use one clock driver output to drive multiple AFEs since the clock buffer’s load capacitance increases by a factor
of N. As a result, the falling and rising time of a clock signal is degraded. A typical clock arrangement for multiple
AFE5808As is illustrated in Figure 90. Each clock buffer output drives one AFE5808A in order to achieve the
best signal integrity and fastest slew rate, i.e. better phase noise performance. When clock phase noise is not a
concern, e.g. the 1×fcw clock in the 16/8/4×fcw operation modes, one clock driver output may excite more than
one AFE5808As. Nevertheless, special considerations should be applied in such a clock distribution network
design. In typical ultrasound systems, it is preferred that all clocks are generated from a same clock source, such
as 16×fcw , 1×fcw clocks, audio ADC clocks, RF ADC clock, pulse repetition frequency signal, frame clock and
etc. By doing this, interference due to clock asynchronization can be minimized
Figure 90. CW Clock Distribution
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