Datasheet

S0503-01
(a) LVPECL Configuration
(c) TransformerBasedConfiguration
(d)CMOS Configuration
(b) LVDSConfiguration
CMOSCLK
Driver
AFE
CMOSCLK
CMOS
AFE
CLOCKs
CLOCK
SOURCE
50 Ω
0.1 Fμ
0.1 Fμ
0.1 Fμ
0.1 Fμ
CDCE72010
AFE
CLOCKs
100 Ω
LVDS
0.1 Fμ
0.1 Fμ
CDCM7005
CDCE7010
AFE
CLOCKs
130 Ω
LVPECL
0.1 Fμ
0.1 Fμ
83 Ω
3.3V
3.3V
130 Ω
AFE5808A
SLOS729B –OCTOBER 2011–REVISED APRIL 2012 www.ti.com
Figure 89. Clock Configurations
The combination of the clock noise and the CW path noise can degrade the CW performance. The internal
clocking circuit is designed for achieving excellent phase noise required by CW operation. The phase noise of
the AFE5808A CW path is better than 155dBc/Hz at 1KHz offset. Consequently the phase noise of the mixer
clock inputs needs to be better than 155dBc/Hz.
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