Datasheet

AFE5808A
SLOS729B –OCTOBER 2011–REVISED APRIL 2012 www.ti.com
PIN INFORMATION
Top View
ZCF (BGA-135)
1 2 3 4 5 6 7 8 9
A AVDD INP8 INP7 INP6 INP5 INP4 INP3 INP2 INP1
B CM_BYP ACT8 ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1
C AVSS INM8 INM7 INM6 INM5 INM4 INM3 INM2 INM1
D AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD AVDD
E CW_IP_AMPINP CW_IP_AMPINM AVSS AVSS AVSS AVSS AVSS AVDD AVDD
F CW_IP_OUTM CW_IP_OUTP AVSS AVSS AVSS AVSS AVSS CLKP_16X CLKM_16X
G AVSS AVSS AVSS AVSS AVSS AVSS AVSS CLKP_1X CLKM_1X
H CW_QP_OUTM CW_QP_OUTP AVSS AVSS AVSS AVSS AVSS PDN_GLOBAL RESET
J CW_QP_AMPINP CW_QP_AMPINM AVSS AVSS AVSS AVDD_ADC AVDD_ADC PDN_VCA SCLK
K AVDD AVDD_5V VCNTLP VCNTLM VHIGH AVSS DNC AVDD_ADC SDATA
L CLKP_ADC CLKM_ADC AVDD_ADC REFM DNC DNC DNC PDN_ADC SEN
M AVDD_ADC AVDD_ADC VREF_IN REFP DNC DNC DNC DNC SDOUT
N D8P D8M DVDD DNC DVSS DNC DVDD D1M D1P
P D7M D6M D5M FCLKM DVSS DCLKM D4M D3M D2M
R D7P D6P D5P FCLKP DVSS DCLKP D4P D3P D2P
PIN FUNCTIONS
PIN
DESCRIPTION
NO. NAME
B9~ B2 ACT1...ACT8 Active termination input pins for CH1~8. 1 μF capacitors are recommended. See the Applicaiton Information section.
A1, D8, D9, E8, AVDD 3.3 V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks.
E9, K1
K2 AVDD_5V 5 V Analog supply for LNA, VCAT, PGA, LPF and CWD blocks.
J6, J7, K8, L3, AVDD_ADC 1.8 V Analog power supply for ADC.
M1, M2
C1, D1~D7,
E3~E7, F3~F7,
AVSS Analog ground.
G1~G7,
H3~H7,J3~J5, K6
Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or through a
L2 CLKM_ADC
0.1 µF capacitor.
Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal directly or through
L1 CLKP_ADC
a 0.1 µF capacitor.
Negative input of differential CW 16X clock. Tie to GND when the CMOS clock mode is enabled. In the 4X and 8X
F9 CLKM_16X CW clock modes, this pin becomes the 4X or 8X CLKM input. In the 1X CW clock mode, this pin becomes the
quadrature-phase 1X CLKM for the CW mixer. Can be floated if CW mode is not used.
Positive input of differential CW 16X clock. In 4X and 8X clock modes, this pin becomes the 4X or 8X CLKP input.
F8 CLKP_16X In the 1X CW clock mode, this pin becomes the quadrature-phase 1X CLKP for the CW mixer. Can be floated if CW
mode is not used.
Negative input of differential CW 1X clock. Tie to GND when the CMOS clock mode is enabled (Refer to Figure 89
G9 CLKM_1X for details). In the 1X clock mode, this pin is the In-phase 1X CLKM for the CW mixer. Can be floated if CW mode is
not used.
Positive input of differential CW 1X clock. In the 1X clock mode, this pin is the In-phase 1X CLKP for the CW mixer.
G8 CLKP_1X
Can be floated if CW mode is not used.
Bias voltage and bypass to ground. ≥1µF is recommended. To suppress the ultra low frequency noise, 10µF can be
B1 CM_BYP
used.
Negative differential input of the In-phase summing amplifier. External LPF capacitor has to be connected between
E2 CW_IP_AMPINM CW_IP_AMPINM and CW_IP_OUTP. This pin becomes the CH7 PGA negative output when PGA test mode is
enabled. Can be floated if not used.
Positive differential input of the In-phase summing amplifier. External LPF capacitor has to be connected between
E1 CW_IP_AMPINP CW_IP_AMPINP and CW_IP_OUTM. This pin becomes the CH7 PGA positive output when PGA test mode is
enabled. Can be floated if not used.
Negative differential output for the In-phase summing amplifier. External LPF capacitor has to be connected
F1 CW_IP_OUTM
between CW_IP_AMPINP andCW_IP_OUTPM. Can be floated if not used.
Positive differential output for the In-phase summing amplifier. External LPF capacitor has to be connected between
F2 CW_IP_OUTP
CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used.
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