Datasheet

I/V
LPF
V/I
Current Clamp
DC Offset
Correction Loop
From attenuator
To ADC
Current Clamp
AFE5808A
www.ti.com SLOS729B –OCTOBER 2011–REVISED APRIL 2012
Figure 68. Simplified Block Diagram of PGA
Low input noise is always preferred in a PGA and its noise contribution should not degrade the ADC SNR too
much after the attenuator. At the minimum attenuation (used for small input signals), the LNA noise dominates; at
the maximum attenuation (large input signals), the PGA and ADC noise dominates. Thus 24 dB gain of PGA
achieves better SNR as long as the amplified signals can exceed the noise floor of the ADC.
The PGA current clamp circuit can be enabled (register 51) to improve the overload recovery performance of the
AFE. If we measure the standard deviation of the output just after overload, for 0.5 V V
CNTL
, it is about 3.2 LSBs
in normal case, i.e the output is stable in about 1 clock cycle after overload. With the current clamp circuit
disabled, the value approaches 4 LSBs meaning a longer time duration before the output stabilizes; however,
with the current clamp circuit enabled, there will be degradation in HD3 for PGA output levels > -2dBFS. For
example, for a –2dBFS output level, the HD3 degrades by approximately 3dB.
The AFE5808A integrates an anti-aliasing filter in the form of a programmable low-pass filter (LPF) in the
transimpedance amplifier. The LPF is designed as a differential, active, 3rd order filter with a typical 18dB per
octave roll-off. Programmable through the serial interface, the –1dB frequency corner can be set to one of
10MHz, 15 MHz, 20 MHz, and 30MHz. The filter bandwidth is set for all channels simultaneously.
A selectable DC offset correction circuit is implemented in the PGA as well. This correction circuit is similar to the
one used in the LNA. It extracts the DC component of the PGA outputs and feeds back to the PGA’s
complimentary inputs for DC offset correction. This DC offset correction circuit also has a high-pass response
with a cut-off frequency of 80 KHz.
ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (ADC) of the AFE5808A employs a pipelined converter architecture that consists
of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error
correction logic, ensuring excellent differential linearity and no missing codes at the 14-bit level. The 14 bits given
out by each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the
AFE5808A operate from a common input clock (CLKP/M). The sampling clocks for each of the eight channels
are generated from the input clock using a carefully matched clock buffer tree. The 14x clock required for the
serializer is generated internally from the CLKP/M pins. A 7x and a 1x clock are also given out in LVDS format,
along with the data, to enable easy data capture. The AFE5808A operates from internally-generated reference
voltages that are trimmed to improve the gain matching across devices. The nominal values of REFP and REFM
are 1.5V and 0.5V, respectively. Alternately, the device also supports an external reference mode that can be
enabled using the serial interface.
Using serialized LVDS transmission has multiple advantages, such as a reduced number of output pins (saving
routing space on the board), reduced power consumption, and reduced effects of digital noise coupling to the
analog circuit inside the AFE5808A.
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