Datasheet

AFE5808A
www.ti.com SLOS729B –OCTOBER 2011–REVISED APRIL 2012
SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing
Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may
not be high. For example, 128 points custom pattern will take approximately 128 x (24 SCLK clock cycles + 4
ADC clock cycles).
NOTE
only one of the above patterns can be active at any given instant.
SYNC_PATTERN: Address: 10[8]
By enabling this bit, all channels' test pattern outputs are synchronized. When 10[8] is set as 1, the ramp
patterns of all 8 channels start simultaneously.
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