Datasheet

AFE5808A
SLOS729B –OCTOBER 2011–REVISED APRIL 2012 www.ti.com
Table 3. Digital HPF –1dB Corner Frequency vs K and Fs
k 40 MSPS 50 MSPS 65 MSPS
2 2780 KHz 3480 KHz 4520 KHz
3 1490 KHz 1860 KHz 2420 KHz
4 770 KHz 960 KHz 1250 KHz
LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
The low-frequency noise suppression mode is especially useful in applications where good noise performance is
desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of
the AFE5808A to approximately Fs/2, thereby moving the noise floor around dc to a much lower value. Register
bit 1[11] is used for enabling or disabling this feature. When this feature is enabled, power consumption of the
device will be increased by approximate 1 mW/CH.
LVDS_OUTPUT_RATE_2X: Address: 1[14]
The output data always uses a DDR format, with valid/different bits on the positive as well as the negative edges
of the LVDS bit clock, DCLK. The output rate is set by default to 1X (LVDS_OUTPUT_RATE_2X = 0), where
each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share one
LVDS stream, in this way lowering the power consumption devoted to the interface. The unused outputs will
output zero. To avoid consumption from those outputs, no termination should be connected to them. The
distribution on the used output pairs is done in the following way:
• Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first.
• Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first.
• Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first.
• Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first
CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
Setting this bit to 1 enables the subtraction of the value on the corresponding OFFSET_CHx<9:0> (offset for
channel i) from the ADC output. The number is specified in 2s-complement format. For example,
OFFSET_CHx<9:0> = 11 1000 0000 means subtract –128. For OFFSET_CHx<9:0> = 00 0111 1111 the effect is
to subtract 127. In effect, both addition and subtraction can be performed. Note that the offset is applied before
the digital gain (see DIGITAL_GAIN_ENABLE). The whole data path is 2s-complement throughout internally, with
digital gain being the last step. Only when ADC_OUTPUT_FORMAT = 1 (straight binary output format) is the 2s-
complement word translated into offset binary at the end.
SERIALIZED_DATA_RATE: Address: 3[14:13]
See Table 1 for detail description.
TEST_PATTERN_MODES: Address: 2[15:13]
The AFE5808A can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal
ADC data output. The device may also be made to output 6 preset patterns:
1. Ramp: Setting Register 2[15:13]=111causes all the channels to output a repeating full-scale ramp pattern.
The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the
full-scale code, it returns back to zero code and ramps again.
2. Zeros: The device can be programmed to output all zeros by setting Register 2[15:13]=110;
3. Ones: The device can be programmed to output all 1s by setting Register 2[15:13]=100;
4. Deskew Patten: When 2[15:13]=010; this mode replaces the 14-bit ADC output with the 01010101010101
word.
5. Sync Pattern: When 2[15:13]=001, the normal ADC output is replaced by a fixed 11111110000000 word.
6. Toggle: When 2[15:13]=101, the normal ADC output is alternating between 1's and 0's. The start state of
ADC word can be either 1's or 0's.
7. Custom Pattern: It can be enabled when 2[15:13]= 011;. Users can write the required VALUE into register
bits <CUSTOM PATTERN> which is Register 5[13:0]. Then the device will output VALUE at its outputs,
about 3 to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24
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