Datasheet

AFE5808A
SLOS729B –OCTOBER 2011–REVISED APRIL 2012 www.ti.com
Table 2. ADC Register Map (continued)
ADDRESS ADDRESS Default
FUNCTION DESCRIPTION
(DEC) (HEX) Value
3[12] 0x3[12] 0 DIGITAL_GAIN_ENABLE 0: No digital gain;
1: Digital gain Enabled
3[14:13] 0x3[14:13] 0 SERIALIZED_DATA_RATE Serialization factor
00: 14x
01: 16x
10: reserved
11: 12x
when 4[1]=1. In the 16x serialization rate, two 0s are filled at two LSBs (see
Table 1)
3[15] 0x3[15] 0 ENABLE_EXTERNAL_ 0: Internal reference mode;
REFERENCE_MODE 1: Set to external reference mode
Note: both 3[15] and 1[13] should be set as 1 when configuring the device in
the external reference mode
4[1] 0x4[1] 0 ADC_RESOLUTION_SELECT 0: 14bit;
1: 12bit
4[3] 0x4[3] 0 ADC_OUTPUT_FORMAT 0: 2's complement;
1: Offset binary
4[4] 0x4[4] 0 LSB_MSB_FIRST 0: LSB first;
1: MSB first
5[13:0] 0x5[13:0] 0 CUSTOM_PATTERN Custom pattern data for LVDS output (2[15:13]=011)
10[8] 0xA[8] 0 SYNC_PATTERN 0: Test pattern outputs of 8 channels are NOT synchronized.
1: Test pattern outputs of 8 channels are synchronized.
13[9:0] 0xD[9:0] 0 OFFSET_CH1 Value to be subtracted from channel 1 code
13[15:11] 0xD[15:11] 0 DIGITAL_GAIN_CH1 0 dB to 6 dB in 0. 2dB steps
15[9:0] 0xF[9:0] 0 OFFSET_CH2 value to be subtracted from channel 2 code
15[15:11] 0xF[15:11] 0 DIGITAL_GAIN_CH2 0dB to 6dB in 0.2 dB steps
17[9:0] 0x11[9:0] 0 OFFSET_CH3 value to be subtracted from channel 3 code
17[15:11] 0x11[15:11] 0 DIGITAL_GAIN_CH3 0 dB to 6 dB in 0.2 dB steps
19[9:0] 0x13[9:0] 0 OFFSET_CH4 value to be subtracted from channel 4 code
19[15:11] 0x13[15:11] 0 DIGITAL_GAIN_CH4 0 dB to 6 dB in 0. 2dB steps
21[0] 0x15[0] 0 DIGITAL_HPF_FILTER_ENABLE 0: Disable the digital HPF filter;
_ CH1-4
1: Enable for 1-4 channels
21[4:1] 0x15[4:1] 0 DIGITAL_HPF_FILTER_K_CH1-4 Set K for the high-pass filter (k from 2 to 10, i.e. 0010B to 1010B).
This group of four registers controls the characteristics of a digital high-pass
transfer function applied to the output data, following the formula:
y(n) = 2
k
/(2
k
+ 1) [x(n) – x(n – 1) + y(n – 1)] (see Table 3 and Figure 58)
25[9:0] 0x19[9:0] 0 OFFSET_CH8 value to be subtracted from channel 8 code
25[15:11] 0x19[15:11] 0 DIGITAL_GAIN_CH8 0 dB to 6 dB in 0.2dB steps
27[9:0] 0x1B[9:0] 0 OFFSET_CH7 value to be subtracted from channel 7 code
27[15:11] 0x1B[15:11] 0 DIGITAL_GAIN_CH7 0 dB to 6dB in 0.2 dB steps
29[9:0] 0x1D[9:0] 0 OFFSET_CH6 value to be subtracted from channel 6 code
29[15:11] 0x1D[15:11] 0 DIGITAL_GAIN_CH6 0 dB to 6 dB in 0.2 dB steps
31[9:0] 0x1F[9:0] 0 OFFSET_CH5 value to be subtracted from channel 5 code
31[15:11] 0x1F[15:11] 0 DIGITAL_GAIN_CH5 0 dB to 6 dB in 0.2 dB steps
33[0] 0x21[0] 0 DIGITAL_HPF_FILTER_ENABLE 0: Disable the digital HPF filter;
_ CH5-8
1: Enable for 5-8 channels
33[4:1] 0x21[4:1] 0 DIGITAL_HPF_FILTER_K_CH5-8 Set K for the high-pass filter (k from 2 to 10, 010B to 1010B)
This group of four registers controls the characteristics of a digital high-pass
transfer function applied to the output data, following the formula:
y(n) = 2
k
/(2
k
+ 1) [x(n) – x(n – 1) + y(n – 1)] (see Table 3 and Figure 58)
66[15] 0x42[15] 0 DITHER 0: Disable dither function.
1: Enable dither function. Improve the ADC linearity with slight noise
degradation.
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