Datasheet

t
1
t
2
t
3
Device Ready for
Serial Register Write
Device Ready for
Data Conversion
Start of Clock
AVDD
AVDD_5V
AVDD_ADC
DVDD
RESET
SEN
CLKP_ADC
t
4
t
7
t
8
t
6
t
5
AFE5808A
SLOS729B –OCTOBER 2011–REVISED APRIL 2012 www.ti.com
10 µs < t1 < 50 ms, 10 µs < t2 < 50 ms, –10 ms < t3 < 10 ms, t4 > 10 ms, t5 > 100 ns, t6 > 100 ns, t7 > 10 ms, and
t8 > 100 µs.
The AVDDx and DVDD power-on sequence does not matter as long as –10ms < t3 < 10ms. Similar considerations
apply while shutting down the device.
Figure 62. Recommended Power-up Sequencing and Reset Timing
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