Datasheet

x
x
x
x x
x x x
x
x
x
x
x
x x
x
A7
A6
A5
A4
A3
A2
A1
A0
SEN
SCLK
SDATA
SDOUT
Start Sequence End Sequence
t
7
t
6
t
2
t
4
t
1
t
5
t
3
D15
D14
D13
D12 D11
D10 D9 D8
D7
D6
D5
D4
D3
D2 D1
D0
t
8
AFE5808A
www.ti.com
SLOS729B OCTOBER 2011REVISED APRIL 2012
SPI Timing Characteristics
Minimum values across full temperature range T
MIN
= 0°C to T
MAX
= 85°C, AVDD_5V =5.0V, AVDD=3.3V,
AVDD_ADC=1.8V, DVDD=1.8V
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
1
SCLK period 50 ns
t
2
SCLK high time 20 ns
t
3
SCLK low time 20 ns
t
4
Data setup time 5 ns
t
5
Data hold time 5 ns
t
6
SEN fall to SCLK rise 8 ns
t
7
Time between last SCLK rising edge to SEN rising edge 8 ns
t
8
SDOUT delay 12 20 28 ns
Register Readout
The device includes an option where the contents of the internal registers can be read back. This may be useful
as a diagnostic test to verify the serial interface communication between the external controller and the AFE.
First, the <REGISTER READOUT ENABLE> bit (Reg0[1]) needs to be set to '1'. Then user should initiate a
serial interface cycle specifying the address of the register (A7-A0) whose content has to be read. The data bits
are "don’t care". The device will output the contents (D15-D0) of the selected register on the SDOUT pin.
SDOUT has a typical delay t8 of 20nS from the falling edge of the SCLK. For lower speed SCLK, SDOUT can be
latched on the rising edge of SCLK. For higher speed SCLK,e.g. the SCLK period lesser than 60nS, it would be
better to latch the SDOUT at the next falling edge of SCLK. The following timing diagram shows this operation
(the time specifications follow the same information provided. In the readout mode, users still can access the
<REGISTER READOUT ENABLE> through SDATA/SCLK/SEN. To enable serial register writes, set the
<REGISTER READOUT ENABLE> bit back to '0'.
Figure 61. Serial Interface Register Read
The AFE5808A SDOUT buffer is tri-stated and will get enabled only when 0[1] (REGISTER READOUT ENABLE)
is enabled. SDOUT pins from multiple AFE5808As can be tied together without any pull-up resistors. Level
shifter SN74AUP1T04 can be used to convert 1.8V logic to 2.5V/3.3V logics if needed.
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