Datasheet
D15
D14
D13
D12 D11
D10 D9 D8
D7
D6
D5
D4
D3
D2 D1
D0
A7
A6
A5
A4
A3
A2
A1
A0
SEN
SCLK
SDATA
RESET
DataLatchedOnRisingEdgeofSCLK
StartSequence
StartSequence
EndSequence
EndSequence
t
7
t
6
t
2
t
4
t
1
t
5
t
3
T0384-01
AFE5808A
SLOS729B –OCTOBER 2011–REVISED APRIL 2012
www.ti.com
LVDS Output Interface Description
AFE5808A has LVDS output interface which supports multiple output formats. The ADC resolutions can be
configured as 12bit or 14bit as shown in the LVDS timing diagrams Figure 59. The ADCs in the AFE5808A are
running at 14bit; 2 LSBs are removed when 12-bit output is selected; and two 0s are added at LSBs when 16-bit
output is selected. Appropriate ADC resolutions can be selected for optimizing system performance-cost
effectiveness. When the devices run at 16bit mode, higher end FPGAs are required to process higher rate of
LVDS data. Corresponding register settings are listed in Table 1.
Table 1. Corresponding Register Settings
LVDS Rate 12 bit (6X DCLK) 14 bit (7X DCLK) 16 bit (8X DCLK)
Reg 3 [14:13] 11 00 01
Reg 4 [2:0] 010 000 000
Description 2 LSBs removed N/A 2 0s added at LSBs
SERIAL REGISTER TIMING
Serial Register Write Description
Programming of different modes can be done through the serial interface formed by pins SEN (serial interface
enable), SCLK (serial interface clock), SDATA (serial interface data) and RESET. All these pins have a pull-down
resistor to GND of 100kΩ. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is
latched at every rising edge of SCLK when SEN is active (low). The serial data is loaded into the register at
every 24th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits
are ignored. Data can be loaded in multiple of 24-bit words within a single active SEN pulse (there is an internal
counter that counts groups of 24 clocks after the falling edge of SEN). The interface can work with the SCLK
frequency from 20 MHz down to low speeds (few Hertz) and even with non-50% duty cycle SCLK. The data is
divided into two main portions: a register address (8 bits) and the data itself (16 bits), to load on the addressed
register. When writing to a register with unused bits, these should be set to 0. Figure 60 illustrates this process.
Figure 60. SPI Timing
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