Datasheet

AFE5808A
www.ti.com SLOS729B –OCTOBER 2011–REVISED APRIL 2012
DIGITAL CHARACTERISTICS
Typical values are at +25°C, AVDD = 3.3 V, AVDD_5 = 5 V and AVDD_ADC = 1.8 V, DVDD = 1.8 V, 14 bit sample rate = 65
MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range: T
MIN
= 0°C to T
MAX
=
+85°C,.
PARAMETER CONDITION MIN TYP MAX UNITS
(1)
DIGITAL INPUTS/OUTPUTS
V
IH
Logic high input voltage 2 3.3 V
V
IL
Logic low input voltage 0 0.3 V
Logic high input current 200 µA
Logic low input current 200 µA
Input capacitance 5 pF
V
OH
Logic high output voltage SDOUT pin DVDD V
V
OL
Logic low output voltage SDOUT pin 0 V
LVDS OUTPUTS
with 100 ohms external differential
Output differential voltage 400 mV
termination
Output offset voltage Common-mode voltage 1100 mV
FCLKP and FCLKM 1X clock rate 10 65 MHz
DCLKP and DCLKM 7X clock rate 70 455 MHz
6X clock rate 60 390 MHz
t
su
Data setup time
(2)
350 ps
t
h
Data hold time
(2)
350 ps
ADC INPUT CLOCK
CLOCK frequency 10 65 MSPS
Clock duty cycle 45% 50% 55%
Sine-wave, ac-coupled 0.5 Vpp
Clock input amplitude,
LVPECL, ac-coupled 1.6 Vpp
differential(V
CLKP_ADC
–V
CLKM_ADC
)
LVDS, ac-coupled 0.7 Vpp
Common-mode voltage biased internally 1 V
Clock input amplitude V
CLKP_ADC
(single-
CMOS CLOCK 1.8 Vpp
ended)
(1) The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1
with 100Ω external termination.
(2) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear
as reduced timing margins
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