Datasheet

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AFE5808A

www.ti.com

SLOS729B –OCTOBER 2011–REVISED APRIL 2012

Fully Integrated, 8-Channel Ultrasound Analog Front End with Passive CW Mixer, 0.75

nV/rtHz, 14/12-Bit, 65 MSPS, 158 mW/CH

Check for Samples: AFE5808A

FEATURES

APPLICATIONS

• 8-Channel Complete Analog Front-End • Medical Ultrasound Imaging

– LNA, VCAT, PGA, LPF, ADC, and CW Mixer • Nondestructive Evaluation Equipments

• Programmable Gain Low-Noise Amplifier

DESCRIPTION

(LNA)

The AFE5808A is a highly integrated Analog Front-

– 24/18/12 dB Gain

End (AFE) solution specifically designed for

– 0.25/0.5/1 V

Linear Input Range

ultrasound systems in which high performance and

– 0.63/0.7/0.9 nV/rtHz Input Referred Noise

small size are required. The AFE5808A integrates a

complete time-gain-control (TGC) imaging path and a

– Programmable Active Termination

continuous wave Doppler (CWD) path. It also enables

• 40 dB Low Noise Voltage Controlled

users to select one of various power/noise

Attenuator (VCAT)

combinations to optimize system performance.

• 24/30 dB Programmable Gain Amplifier (PGA)

Therefore, the AFE5808A is a suitable ultrasound

analog front end solution not only for high-end

• 3

Order Linear Phase Low-Pass Filter (LPF)

systems, but also for portable ones.

– 10, 15, 20, 30 MHz

The AFE5808A contains eight channels of voltage

• 14-bit Analog to Digital Converter (ADC)

controlled amplifier (VCA), 14/12-bit Analog-to-Digital

– 77 dBFS SNR at 65 MSPS

Converter (ADC), and CW mixer. The VCA includes

– LVDS Outputs

Low noise Amplifier (LNA), Voltage controlled

Attenuator (VCAT), Programmable Gain Amplifier

• Noise/Power Optimizations (Full Chain)

(PGA), and Low-Pass Filter (LPF). The LNA gain is

– 158 mW/CH at 0.75 nV/rtHz, 65 MSPS

programmable to support 250 mV

to 1 V

input

– 101 mW/CH at 1.1 nV/rtHz, 40 MSPS

signals. Programmable active termination is also

supported by the LNA. The ultra-low noise VCAT

– 80 mW/CH at CW Mode

provides an attenuation control range of 40 dB and

• Excellent Device-to-Device Gain Matching

improves overall low gain SNR which benefits

– ±0.5 dB (Typical) and ±0.9 dB (Max)

harmonic imaging and near field imaging. The PGA

provides gain options of 24 dB and 30 dB. Before the

• Low Harmonic Distortion

ADC, a LPF can be configured as 10 MHz, 15 MHz,

• Fast and Consistent Overload Recovery

20 MHz or 30 MHz to support ultrasound applications

• Passive Mixer for Continuous Wave

with different frequencies. The high-performance

Doppler(CWD)

14bit/65 MSPS ADC in the AFE5808A achieves

77dBFS SNR. It ensures excellent SNR at low chain

– Low Close-in Phase Noise –156 dBc/Hz at 1

gain. The ADC’s LVDS outputs enable flexible system

KHz off 2.5 MHz Carrier

integration desired for miniaturized systems.

– Phase Resolution of 1/16λ

– Support 16X, 8X, 4X and 1X CW Clocks

– 12dB Suppression on 3

and 5

Harmonics

– Flexible Input Clocks

• Small Package: 15 mm x 9 mm, 135-BGA

NOTE

AFE5808A is an enhanced version of AFE5808 and it is recommended for new designs.

Compared to AFE5808, it expands the cut-off frequency range of the digital high pass

filter; increases the handling capability of extreme overload signals; lowers the correlated

noise significantly when high impedance source appears.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (66 pages)

PAGE 1
AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 Fully Integrated, 8-Channel Ultrasound Analog Front End with Passive CW Mixer, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 158 mW/CH Check for Samples: AFE5808A FEATURES APPLICATIONS • • • 1 • • • • • • • • • • • 8-Channel Complete Analog Front-End – LNA, VCAT, PGA, LPF, ADC, and CW Mixer Programmable Gain Low-Noise Amplifier (LNA) – 24/18/12 dB Gain – 0.25/0.5/1 VPP Linear Input Range – 0.63/0.7/0.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range VALUE UNIT AVDD –0.3 to 3.9 V AVDD_ADC –0.3 to 2.2 V –0.3 to 6 V –0.3 to 2.2 V –0.3 to 0.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 PIN FUNCTIONS (continued) PIN DESCRIPTION NO. NAME J2 CW_QP_AMPINM Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be connected between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative output when PGA test mode is enabled. Can be floated if not used. J1 CW_QP_AMPINP Positive differential input of the quadrature-phase summing amplifier.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 DIGITAL CHARACTERISTICS Typical values are at +25°C, AVDD = 3.3 V, AVDD_5 = 5 V and AVDD_ADC = 1.8 V, DVDD = 1.8 V, 14 bit sample rate = 65 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = 0°C to TMAX = +85°C,. PARAMETER CONDITION MIN TYP MAX UNITS (1) DIGITAL INPUTS/OUTPUTS VIH Logic high input voltage 2 VIL Logic low input voltage 0 3.3 V 0.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, ac-coupled with 0.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) Impedance Magnitude Response Impedance Phase Response 10 Open 12000 −10 Phase (Degrees) 10000 Impedance (Ohms) Open 0 8000 6000 4000 −20 −30 −40 −50 −60 −70 2000 −80 500k 4.5M 8.5M 12.5M 16.5M −90 500k 20.5M 4.5M 8.5M Frequency (Hz) 20.5M Figure 9.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) HPF CHARACTERISTICS (LNA+VCA+PGA+ADC) −146 −148 −5 −150 Phase Noise (dBc/Hz) 0 Amplitude (dB) −10 −15 −20 −25 −30 16X Clock Mode 8X Clock Mode 4X Clock Mode −152 −154 −156 −158 −160 −162 −164 −166 −35 −40 Single Channel CW PN −144 5 −168 10 100 −170 100 500 1000 Frequency (KHz) Figure 15.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) Hz) 60 4.0 LNA 12 dB LNA 18 dB LNA 24 dB 50 Input reffered noise (nV Input reffered noise (nV Hz) 70 40 30 20 10 2.0 1.5 1.0 0.1 0.2 Vcntl (V) 0.3 0.4 Figure 21. IRN, PGA = 24 dB and Medium Power Mode 70 4.0 Hz) 60 LNA 12 dB LNA 18 dB LNA 24 dB 50 40 30 20 10 190 LNA 12 dB LNA 18 dB LNA 24 dB Output reffered noise (nV 170 150 130 110 90 70 50 30 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com 1.5 LNA 12 dB LNA 18 dB LNA 24 dB 1.4 Hz) 1.3 Amplitude (nV Output reffered noise (nV Hz) TYPICAL CHARACTERISTICS (continued) 340 320 300 280 260 240 220 200 180 160 140 120 100 80 60 40 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Vcntl (V) 1 0.3 1.0 1.1 1.2 Figure 26. ORN, PGA = 24 dB and Low Power Mode 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequency (MHz) 9.0 10.0 11.0 12.0 Figure 27.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) 9 10 100 ohm act term 200 ohm act term 400 ohm act term Without Termination 8 8 Noise Figure (dB) Noise Figure (dB) 7 6 5 4 3 7 6 5 4 3 2 2 1 1 0 50 100 150 200 50 ohm act term 100 ohm act term 200 ohm act term 400 ohm act term Without Termination 9 250 300 350 0 400 50 100 150 Source Impedence (Ω) Figure 32.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) −45 −40 Low noise Low power Medium power −50 −50 −55 HD2 (dBc) −55 HD3 (dBc) Low noise Low power Medium power −45 −60 −65 −60 −65 −70 −75 −80 −70 −85 −75 1 2 3 4 5 6 7 Frequency (MHz) 8 9 −90 10 18 24 30 36 Figure 39. HD2 vs.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) −50 −40 Fin1=2MHz, Fin2=2.01MHz Fin1=5MHz, Fin2=5.01MHz Low noise Low power Medium power −54 IMD3 (dBFS) −50 HD3 (dB) −60 −70 −58 −62 −66 −80 −70 −90 18 21 24 27 30 33 36 Gain (dB) 39 42 45 14 18 22 48 Figure 44. HD3 vs. Gain, LNA = 24 dB and PGA = 24 dB and VOUT = -1 dBFS 26 30 Gain (dB) 42 G001 PSMR vs SUPPLY FREQUENCY Fin1=2MHz, Fin2=2.01MHz Fin1=5MHz, Fin2=5.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com 20000.0 −20 Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 −40 16000.0 14000.0 Output Code PSRR wrt supply tone (dB) −30 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 3.0 Output Code Vcntl 18000.0 −50 −60 12000.0 10000.0 8000.0 6000.0 4000.0 −70 2000.0 −80 −90 0.0 0.0 5 10 100 0.5 1.0 1.5 Time (µs) 2.0 2.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) 10000 2000 47nF 15nF 6000 1200 4000 800 2000 0 −2000 400 0 −400 −4000 −800 −6000 −1200 −8000 −1600 −10000 0 0.5 1 1.5 2 2.5 3 Time (µs) 3.5 4 4.5 47nF 15nF 1600 Output Code Output Code 8000 −2000 5 Figure 56. Overload Recovery Response vs. INM Capacitor, VIN = 50 mVPP/100 µVPP, Max Gain 1 1.5 2 2.5 3 3.5 Time (µs) 4 4.5 5 Figure 57. Overload Recovery Response vs.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com TIMING CHARACTERISTICS (1) Typical values are at 25°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, Differential clock, CLOAD = 5pF, RLOAD = 100 Ω, 14Bit, sample rate = 65MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range TMIN = 0°C to TMAX = 85°C with AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.
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12-Bit 6x serialization mode Output Data CHnOUT Data rate = 14 x fCLKIN Bit Clock DCLK Freq = 7 x fCLKIN Frame Clock FCLK Freq = fCLKIN Input Clock CLKIN Freq = fCLKIN Input Signal D0 D13 D12 D1 (D12) (D13) (D0) (D1) D11 (D2) Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: AFE5808A D13 (D0) D10 D9 (D3) (D4) D6 D5 (D7) (D8) Output Data Pair Bit Clock CHi out tsu DCLKM th D11 D10 (D2) (D3) Dn D7 D6 (D6) (D7) SAMPLE N-1 D9 D8 (D4) (D5) Sample N+Cd ta Dn + 1 t
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com LVDS Output Interface Description AFE5808A has LVDS output interface which supports multiple output formats. The ADC resolutions can be configured as 12bit or 14bit as shown in the LVDS timing diagrams Figure 59. The ADCs in the AFE5808A are running at 14bit; 2 LSBs are removed when 12-bit output is selected; and two 0s are added at LSBs when 16-bit output is selected.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 SPI Timing Characteristics Minimum values across full temperature range TMIN = 0°C to TMAX = 85°C, AVDD_5V =5.0V, AVDD=3.3V, AVDD_ADC=1.8V, DVDD=1.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com t1 AVDD AVDD_5V AVDD_ADC t2 DVDD t3 t4 t7 t5 RESET t6 Device Ready for Serial Register Write SEN Start of Clock Device Ready for Data Conversion CLKP_ADC t8 10 µs < t1 < 50 ms, 10 µs < t2 < 50 ms, –10 ms < t3 < 10 ms, t4 > 10 ms, t5 > 100 ns, t6 > 100 ns, t7 > 10 ms, and t8 > 100 µs. The AVDDx and DVDD power-on sequence does not matter as long as –10ms < t3 < 10ms. Similar considerations apply while shutting down the device.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 REGISTER MAP A reset process is required at the AFE5808A initialization stage. Initialization can be done in one of two ways: 1. Through a hardware reset, by applying a positive pulse in the RESET pin 2. Through a software reset, using the serial interface, by setting the SOFTWARE RESET bit to high.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com Table 2. ADC Register Map (continued) ADDRESS (DEC) ADDRESS (HEX) Default Value 3[12] 0x3[12] 0 DIGITAL_GAIN_ENABLE 0: No digital gain; 1: Digital gain Enabled 3[14:13] 0x3[14:13] 0 SERIALIZED_DATA_RATE Serialization factor 00: 14x 01: 16x 10: reserved 11: 12x when 4[1]=1.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 ADC Register/Digital Processing Description The ADC in the AFE5808A has extensive digital processing functionalities which can be used to enhance ultrasound system performance. The digital processing blocks are arranged as in Figure 63. ADC Output Channel Average Default=No 12/14b Digital Gain Default=0 Digital HPF Default = No 12/14b Final Digital Output Digital Offset Default=No Figure 63.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com Table 3. Digital HPF –1dB Corner Frequency vs K and Fs k 40 MSPS 50 MSPS 65 MSPS 2 2780 KHz 3480 KHz 4520 KHz 3 1490 KHz 1860 KHz 2420 KHz 4 770 KHz 960 KHz 1250 KHz LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11] The low-frequency noise suppression mode is especially useful in applications where good noise performance is desired in the frequency band of 0MHz to 1MHz (around dc).
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may not be high. For example, 128 points custom pattern will take approximately 128 x (24 SCLK clock cycles + 4 ADC clock cycles). NOTE only one of the above patterns can be active at any given instant.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com VCA Register Map Table 4. VCA Register Map ADDRESS (DEC) ADDRESS (HEX) Default Value FUNCTION DESCRIPTION 51[0] 0x33[0] 0 RESERVED 0 51[3:1] 0x33[3:1] 0 LPF_PROGRAMMABILITY 000: 15MHz, 010: 20MHz, 011: 30MHz, 100: 10MHz 51[4] 0x33[4] 0 PGA_INTEGRATOR_DISABLE (PGA_HPF_DISABLE) 0: Enable 1: Disables offset integrator for PGA.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 Table 4. VCA Register Map (continued) ADDRESS (DEC) ADDRESS (HEX) Default Value FUNCTION DESCRIPTION 53[11] 0x35[11] 0 MED_POWER 0: Low noise mode; 1: Sets to medium power mode(53[10]=0). At 30dB PGA, total chain gain may slightly change.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com Table 4. VCA Register Map (continued) ADDRESS (DEC) ADDRESS (HEX) Default Value FUNCTION DESCRIPTION 59[8] 0x3B[8] 0 CW_SUM_AMP_PDN 0: Power down; 1: Normal operation Note: 59[8] is only effective in TGC test mode.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 Programmable Gain for CW Summing Amplifier Different gain can be configured for the CW summing amplifier through the register 54[4:0]. By enabling and disabling the feedback resistors between the summing amplifier inputs and outputs, the gain is adjustable accordingly to maximize the dynamic range of CW path. Table 7 describes the relationship between the summing amplifier gain and 54[4:0] settings. Table 7.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com THEORY OF OPERATION AFE5808A OVERVIEW The AFE5808A is a highly integrated Analog Front-End (AFE) solution specifically designed for ultrasound systems in which high performance and small size are required. The AFE5808A integrates a complete time-gaincontrol (TGC) imaging path and a continuous wave Doppler (CWD) path. It also enables users to select one of various power/noise combinations to optimize system performance.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 The AFE5808A can be terminated passively or actively. Active termination is preferred in ultrasound application for reducing reflection from mismatches and achieving better axial resolution without degrading noise figure too much. Active termination values can be preset to 50, 100, 200, 400Ω; other values also can be programmed by users through register 52[4:0].
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com A1 - A7 Attenuator Stages Attenuator Input RS Attenuator Output Q1 VB A1 Q2 A1 Q3 A1 C1 C2 V1 Q4 A1 C3 V2 Q5 A1 C4 V3 Q6 A1 C5 V4 Q7 A1 C6 V5 C7 V6 V7 VCNTL C1 - C8 Clipping Amplifiers Control Input Figure 66. Simplified Voltage Controlled Attenuator (Analog Structure) Attenuator Input RS Attenuator Output Q1 Q2 Q3 Q4 Q5 SW5 SW6 Q6 Q7 VB SW1 SW2 SW3 SW4 SW7 VHIGH Figure 67.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 Current Clamp From attenuator To ADC I/V LPF V/I Current Clamp DC Offset Correction Loop Figure 68. Simplified Block Diagram of PGA Low input noise is always preferred in a PGA and its noise contribution should not degrade the ADC SNR too much after the attenuator. At the minimum attenuation (used for small input signals), the LNA noise dominates; at the maximum attenuation (large input signals), the PGA and ADC noise dominates.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com CONTINUOUS-WAVE (CW) BEAMFORMER Continuous-wave Doppler is a key function in mid-end to high-end ultrasound systems. Compared to the TGC mode, the CW path needs to handle high dynamic range along with strict phase noise performance. CW beamforming is often implemented in analog domain due to the mentioned strict requirements.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 ACT1 500Ω IN1 INPUT1 INM1 Mixer Clock 1 LNA1 Cext 500Ω ACT2 500Ω IN2 INPUT2 INM2 Mixer Clock 2 CW_AMPINM 10Ω 10Ω LNA2 500Ω Rint/Rext CW_OUTP I/V Sum Amp Rint/Rext CW _AMPINP CW_OUTM Cext CW I or Q CHANNEL Structure ACT8 500Ω IN8 INPUT8 INM8 Mixer Clock 8 LNA8 500Ω Note: the 10Ω resistors at CW_AMPINM/P are due to internal IC routing and can create slight attenuation. Figure 70.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com From the above equations, the 3rd and 5th order harmonics from the LO can interface with the 3rd and 5th order harmonic signals in the Vi(t); or the noise around the 3rd and 5th order harmonics in the Vi(t). Therefore, the mixer’s performance is degraded. In order to eliminate this side effect due to the square-wave demodulation, a proprietary harmonic suppression circuit is implemented in the AFE5808A.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 Fin 16X Clock INV D Q Fin 1X Clock Fin 1X Clock 16 Phase Generator 1X Clock Phase 0º 1X Clock Phase 22.5º SPI 1X Clock Phase 292.5º 1X Clock Phase 315º 1X Clock Phase 337.5º 16-to-8 Cross Point Switch Mixer 1 1X Clock Mixer 2 1X Clock Mixer 3 1X Clock Mixer 6 1X Clock Mixer 7 1X Clock Mixer 8 1X Clock Figure 72. Fin 1X Clock Fin 16X Clock 1X Clock Phase 0° 1X Clock Phase 22.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com INV 4X/8X Clock I/Q CLK Generator D Q 1X Clock LNA2~8 In-phase CLK Summed In-Phase Quadrature CLK I/V Weight Weight LNA1 I/V Weight Summed Quadrature Weight Figure 74. 8 X ƒcw and 4 X ƒcw Block Diagram Fin 1X Clock Fin 4X Clock 1X Clock Phase 0° 1X Clock Phase 90° Quadrature clocks Figure 75.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 EQUIVALENT CIRCUITS CM CM (a) INP (b) INM (c) ACT S0492-01 Figure 77. Equivalent Circuits of LNA inputs S0493-01 Figure 78. Equivalent Circuits of VCNTLP/M VCM 5 kΩ 5 kΩ CLKP CLKM (a) CW 1X and 16X Clocks (b) ADC Input Clocks S0494-01 Figure 79.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com (a) CW_OUTP/M (b) CW_AMPINP/M S0495-01 Figure 80. Equivalent Circuits of CW Summing Amplifier Inputs and Outputs – Low + +Vdiff High AFE5808A OUTP + – + –Vdiff – High Vcommon Low External 100-W Load Rout OUTM Switch impedance is nominally 50 W (±10%) Figure 81.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 APPLICATION INFORMATION 0.1μF AVSS IN CH2 IN CH3 IN CH4 IN CH5 IN CH6 IN CH7 IN CH8 1.4V 0.1μF DVDD AVDD N*0.1μF AVSS 1.8VD N*0.1μF DVSS D1M 0.1μF 15nF IN1M D2P 0.1μF 1μF ACT2 D2M 0.1μF IN2P D3P 15nF IN2M D3M 1μF ACT3 D4P 0.1μF CLKP_1X 0.1μF CLKM_1X CLKP CLKM 0.1μF CLKP_16X 0.1μF 0.1μF IN3P D4M 15nF IN3M D5P 1μF ACT4 D5M 0.1μF IN4P D6P 15nF IN4M D6M 1μF ACT5 0.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com A typical application circuit diagram is listed above. The configuration for each block is discussed below. LNA CONFIGURATION LNA Input Coupling and Decoupling The LNA closed-loop architecture is internally compensated for maximum stability without the need of external compensation components. The LNA inputs are biased at 2.4 V and AC coupling is required. A typical input configuration is shown in Figure 83.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 CM_BYP and VHIGH pins, which generate internal reference voltages, need to be decoupled with ≥1uF capacitors. Bigger bypassing capacitors (>2.2uF) may be beneficial if low frequency noise exists in system. LNA Noise Contribution The noise spec is critical for LNA and it determines the dynamic range of entire system. The LNA of the AFE5808A achieves low power and an exceptionally low-noise voltage of 0.63 nV/√Hz, and a low current noise of 2.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com Under the no termination configuration, the input impedance of the AFE5808A is about 6KΩ (8 K//20 pF) at 1 MHz. Passive termination requires external termination resistor Rt, which contributes to additional thermal noise. The LNA supports active termination with programmable values, as shown in Figure 85 . 450Ω 900Ω 1800Ω ACTx 3600Ω 4500Ω INPx Input INMx LNAx AFE S0500-01 Figure 85.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 LNA Gain Switch Response The LNA gain is programmable through SPI. The gain switching time depends on the SPI speed as well as the LNA gain response time. During the switching, glitches might occur and they can appear as artifacts in images. LNA gain switching in a single imaging line may not be preferred, although digital signal processing might be used here for glitch suppression.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com As discussed in the theory of operation, the attenuator architecture uses seven attenuator segments that are equally spaced in order to approximate the linear-in-dB gain-control slope. This approximation results in a monotonic slope; the gain ripple is typically less than ±0.5dB. The control voltage input (VCNTLM/P pins) represents a high-impedance input.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 CW OPERATION CW Summing Amplifier In order to simplify CW system design, a summing amplifier is implemented in the AFE5808A to sum and convert 8-channel mixer current outputs to a differential voltage output. Low noise and low power are achieved in the summing amplifier while maintaining the full dynamic range required in CW operation.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com CEXT REXT 250Ω 250Ω RINT 500Ω 1000Ω 2000Ω CW_AMPINP CW_AMPINM CW_OUTM I/V Sum Amp CW_OUTP 250Ω 250Ω 500Ω RINT 1000Ω 2000Ω REXT CEXT S0501-01 Figure 87. CW Summing Amplifier Block Diagram Multiple AFE5808As are usually utilized in parallel to expand CW beamformer channel count. These AFE5808As’ CW outputs can be summed and filtered externally further to achieve desired gain and filter response.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 AFE No.4 AFE No.3 AFE No.2 ACT1 500 Ω INP1 INPUT1 INM1 AFE No.1 Mixer 1 Clock LNA1 500 Ω ACT2 500 Ω INP2 INPUT2 INM2 Ext Sum Amp Cext Mixer 2 Clock Rint/Rext CW_AMPINP CW_AMPINM LNA2 I/V Sum Amp CW_OUTM CW_OUTP Rint/Rext 500 Ω CAC RSUM Cext CW I or Q CHANNEL Structure ACT8 500 Ω INP8 INPUT8 INM8 Mixer 8 Clock LNA8 500 Ω S0502-01 Figure 88.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com 3.3 V 130 Ω 83 Ω CDCM7005 CDCE7010 3.3 V 0.1 μF AFE CLOCKs 0.1 μF 130 Ω LVPECL (a) LVPECL Configuration 100 Ω CDCE72010 0.1 μF 0.1 μF AFE CLOCKs LVDS (b) LVDS Configuration 0.1μF 0.1μF CLOCK SOURCE 0.1μF AFE CLOCKs 50 Ω 0.1μF (c) Transformer Based Configuration CMOS CLK Driver AFE CMOS CLK CMOS (d) CMOS Configuration S0503-01 Figure 89.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 In the 16/8/4×fcw operations modes, low phase noise clock is required for 16/8/4×ƒcw clocks (i.e. CLKP_16X/ CLKM_16X pins) in order to maintain good CW phase noise performance. The 1×ƒcw clock (i.e. CLKP_1X/ CLKM_1X pins) is only used to synchronize the multiple AFE5808A chips and is not used for demodulation. Thus 1×fcw clock’s phase noise is not a concern.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com CW Supporting Circuits As a general practice in CW circuit design, in-phase and quadrature channels should be strictly symmetrical by using well matched layout and high accuracy components. In systems, additional high-pass wall filters (20Hz to 500Hz) and low-pass audio filters (10KHz to 100KHz) with multiple poles are usually needed. Since CW Doppler signal ranges from 20Hz to 20KHz, noise under this range is critical.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 The AFE5808A ADC clock input can be driven by differential clocks (sine wave, LVPECL or LVDS) or singled clocks (LVCMOS) similar to CW clocks as shown in Figure 89. In the single-end case, it is recommended that the use of low jitter square signals (LVCMOS levels, 1.8V amplitude). See TI document SLYT075 for further details on the theory.
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com Partial Power-Up/Down Mode The partial power up/down mode is also called as fast power up/down mode. In this mode, most amplifiers in the signal path are powered down, while the internal reference circuits remain active as well as the LVDS clock circuit, i.e. the LVDS circuit still generates its frame and bit clocks. The partial power down function allows the AFE5808A to be wake up from a low-power state quickly.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 Some registers are related to this test mode. PGA Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down Reg59[8]; and Buffer Amplifier Gain Control Reg54[4:0].
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AFE5808A SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com All bypassing and power supplies for the AFE5808A should be referenced to their corresponding ground planes. All supply pins should be bypassed with 0.1µF ceramic chip capacitors (size 0603 or smaller). In order to minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible. Where double-sided component mounting is allowed, these capacitors are best placed directly under the package.
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AFE5808A www.ti.com SLOS729B – OCTOBER 2011 – REVISED APRIL 2012 REVISION HISTORY Changes from Original (October 2011) to Revision A Page • Moved footnote "Low Noise Mode/Medium Power Mode/Low Power Mode" to the test condition for Input Referred Current Noise ........................................................................................................................................................................ 6 • Changed CW signal carrier freq From 8 MHz Max To 8 MHz typical .........
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) AFE5808AZCF ACTIVE Package Type Package Pins Package Drawing Qty NFBGA ZCF 135 160 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) SNAGCU Level-3-260C-168 HR (4) 0 to 85 AFE5808A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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