Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TIMING CHARACTERISTICS
- LVDS OUTPUT TIMING CHARACTERISTICS
- LVDS OUTPUT TIMING CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- SERIAL INTERFACE
- SERIAL REGISTER MAP
- SUMMARY OF FEATURES
- DESCRIPTION OF SERIAL REGISTERS
- THEORY OF OPERATION
- APPLICATION INFORMATION
- REVISION HISTORY
AFE5805
www.ti.com
SBOS421D –MARCH 2008–REVISED MARCH 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October, 2008) to Revision D Page
• Changed Output transconductance specification notation from V/I to I
OUT
/V
IN
..................................................................... 4
• Changed Input clock (FCLK) rising edge to ADC input clock for Clock propagation delay parameter description ............ 13
• Changed Input clock (FCLK) rising edge to ADC input clock for Clock propagation delay parameter description ............ 13
• Corrected PD polarity and notation in Figure 38 ................................................................................................................ 20
• Changed CS input line connection to SPI interface and register block in Figure 41 .......................................................... 21
• Changed footnote 2 for Table 2 .......................................................................................................................................... 23
• Changed ADC_RESET to ADS_RESET in VCA Reset section ......................................................................................... 25
• Changed hyperlink pointer in paragraph five of Power-Down Modes section .................................................................... 29
• Changed last sentence of second paragraph in CLOCK JITTER, POWER NOISE, SNR, AND LVDS TIMING ............... 47
• Added 02, 0080h to Table 19 ............................................................................................................................................. 47
• Changed note a; updated values of current increase from 4mW to 8mW and 0.6mA to 1.9mA ....................................... 47
Changes from Revision B (July, 2008) to Revision C Page
• Corrected V
CM
subscript for common-mode voltage (internal) and V
CM
output current ........................................................ 4
• Changed AVDD2 to AVDD1 in description of pin L9 .......................................................................................................... 10
• Added statement about register initialization to Register Initialization section ................................................................... 21
• Changed bit D7 for address 42; added values of '1' for all four functions .......................................................................... 24
• Changed VCM pin to CM pin .............................................................................................................................................. 24
• Revised External Reference section, Equation 1 and Equation 2 to reflect CM pin instead of VCM pin ........................... 33
• Corrected second paragraph of Analog-to-Digital Conversion section to change VCM to CM .......................................... 40
• Changed total input capacitance description from 30pF to 16pF ....................................................................................... 41
• Changed VCM to CM .......................................................................................................................................................... 45
• Changed common-mode voltage VCM to V
CM
and related references to CM pin, including Equation 3 and
Equation 4 ........................................................................................................................................................................... 46
• Changed VCM to V
CM
......................................................................................................................................................... 47
• Added CLOCK JITTER, POWER NOISE, SNR, AND LVDS TIMING, Clock Jitter, Power Noise, SNR, and LVDS
Timing ................................................................................................................................................................................. 47
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