Datasheet

AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com
GROUNDING AND BYPASSING High-speed mixed signal devices are sensitive to
various types of noise coupling. One primary source
The AFE5805 distinguishes between three different
of noise is the switching noise from the serializer and
grounds: AVSS1 and AVSS2 (analog grounds), and
the output buffer/drivers. For the AFE5805, care has
LVSS (digital ground). In most cases, it should be
been taken to ensure that the interaction between the
adequate to lay out the printed circuit board (PCB) to
analog and digital supplies within the device is kept to
use a single ground plane for the AFE5805. Care
a minimal amount. The extent of noise coupled and
should be taken that this ground plane is properly
transmitted from the digital and analog sections
partitioned between various sections within the
depends on the effective inductances of each of the
system to minimize interactions between analog and
supply and ground connections. Smaller effective
digital circuitry. Alternatively, the digital (LVDS)
inductance of the supply and ground pins leads to
supply set consisting of the LVDD and LVSS pins can
improved noise suppression. For this reason, multiple
be placed on separate power and ground planes. For
pins are used to connect each supply and ground
this configuration, the AVSS and LVSS grounds
sets. It is important to maintain low inductance
should be tied together at the power connector in a
properties throughout the design of the PCB layout by
star layout.
use of proper planes and layer thickness.
All bypassing and power supplies for the AFE5805
should be referenced to this analog ground plane. All BOARD LAYOUT
supply pins should be bypassed with 0.1mF ceramic
Proper grounding and bypassing, short lead length,
chip capacitors (size 0603 or smaller). In order to
and the use of ground and power-supply planes are
minimize the lead and trace inductance, the
particularly important for high-frequency designs.
capacitors should be located as close to the supply
Achieving optimum performance with a
pins as possible. Where double-sided component
high-performance device such as the AFE5805
mounting is allowed, these capacitors are best placed
requires careful attention to the PCB layout to
directly under the package. In addition, larger bipolar
minimize the effects of board parasitics and optimize
decoupling capacitors (2.2mF to 10mF, effective at
component placement. A multilayer PCB usually
lower frequencies) may also be used on the main
ensures best results and allows convenient
supply pins. These components can be placed on the
component placement.
PCB in proximity (< 0.5in or 12.7mm) to the AFE5805
itself.
In order to maintain proper LVDS timing, all LVDS
traces should follow a controlled impedance design
The AFE5805 internally generates a number of
(for example, 100Ω differential). In addition, all LVDS
reference voltages, such as the bias voltages (VB1
trace lengths should be equal and symmetrical; it is
through VB6). Note that in order to achieve optimal
recommended to keep trace length variations less
low-noise performance, the VB1 pin must be
than 150mil (0.150in or 3.81mm).
bypassed with a capacitor value of at least 1mF; the
recommended value for this bypass capacitor is
Additional details on PCB layout techniques can be
2.2mF. All other designed reference pins can be
found in the Texas Instruments Application Report
bypassed with smaller capacitor values, typically
MicroStar BGA Packaging Reference Guide
0.1mF. For best results choose low-inductance
(SSYZ015B), which can be downloaded from the TI
ceramic chip capacitors (size 402) and place them as
web site (www.ti.com).
close as possible to the device pins as possible.
48 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): AFE5805