Datasheet

AFE5805
www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010
Table 18. State of Reference Voltages for Various Combinations of ADS_PD and INT/EXT
PIN, REGISTER BIT INTERNAL BUFFER STATE
ADS_PD pin 0 0 1 1 0 0 1 1
INT/EXT pin 0 1 0 1 0 1 0 1
EXT_REF_VCM 0 0 0 0 1 1 1 1
REFT buffer 3-state 2.5V 3-state 2.5V
(1)
1.5V + V
CM
/1.5V Do not use 2.5V
(1)
Do not use
REFB buffer 3-state 0.5V 3-state 0.5V
(1)
1.5V – V
CM
/1.5V Do not use 0.5V
(1)
Do not use
CM pin 1.5V 1.5V 1.5V 1.5V Force Do not use Force Do not use
(1) Weakly forced with reduced strength.
Poor RMS jitter (> 100ps), combined with inadequate
power-supply design (for example, supply voltage
POWER SUPPLIES
drops and ripple increases), can affect LVDS timing.
The AFE5805 operates on three supply rails: a digital
As a result, occasional glitches might be observed on
1.8V supply, and the 3.3V and 5V analog supplies. At
the AFE5805 outputs. If this phenomenon is
initial power-up, the part is operational in TGC mode,
observed, or if clock jitter and LVDD noise are
with the registers in the respective default
concerns in the overall system, the registers
configurations (see Table 2).
described in Table 19 can be written as part of the
initialization sequence in order to stabilize LVDS
In TGC mode, only the VCA (attenuator) draws a low
clock timing and SNR performance.
current (typically 8mA) from the 5V supply. Switching
into the CW mode, the internal V/I-amplifiers are then
Table 19. Address and Data in Hexadecimal
powered from the 5V rails as well, raising the
operating current on the 5V rail. At the same time, the
ADDRESS DATA
post-gain amplifiers (PGA) are being powered down,
01 0010h
thereby reducing the current consumption on the 3.3V
D1 0140h
rail (refer to the Electrical Characteristics table for
DA 0001h
details on TGC mode and CW mode current
consumption).
E1 0020h
02 0080h
All analog supply rails for the AFE5805 should be low
01 0000h
noise, including the 3.3V digital supply DVDD that
connects to the internal logic blocks of the VCA within
Writing to these registers has the following additional
the AFE5805. It is recommended to tie the DVDD
effects:
pins to the same 3.3V analog supply as the AVDD1/2
pins, rather than a different 3.3V rail that may also
a. Total chip power increases by approximately
provide power to other logic device in the system.
8mW—this includes a current increase of about
Transients and noise generated by those devices can
1.9mA on AVDD1 and about 1.1mA on LVDD.
couple into the AFE5805 and degrade overall device
b. With reference to the LVDS Timing Diagram and
performance.
the Definition of Setup and Hold Times,
LCLKP/LCLKM shift by about 100ps to the left
CLOCK JITTER, POWER NOISE, SNR, AND
relative to CLK and OUTP/OUTM. This shift
LVDS TIMING
causes the data setup time to reduce by 100ps
and the data hold time to increase by 100ps.
As explained in application note SLYT075, ADC clock
c. The clock propagation delay (t
PROP
) is reduced by
jitter can degrade ADC performance. Therefore, it is
approximately 2ns. The typical and minimum
always preferred to use a low jitter clock to drive the
values for this specification are reduced by 2ns,
AFE5805. To ensure the performance of the
and the maximum value is reduced by 1.5ns.
AFE5805, a clock with a jitter of 1ps RMS or better is
expected. However, it might not be always possible to
Power-supply noise usually can be minimized if
use this clock configuration for practical reasons. With
grounding, bypassing, and printed circuit board (PCB)
a higher clock jitter, the SNR of the AFE5805 may be
layout are well managed. Some guidelines can be
degraded as well as the LVDS timing stability. In
found in the Grounding and Bypassing and Board
addition, clean and stable power supplies are always
Layout sections.
preferred to maximize device SNR performance and
ensure LVDS timing stability.
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