Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TIMING CHARACTERISTICS
- LVDS OUTPUT TIMING CHARACTERISTICS
- LVDS OUTPUT TIMING CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- SERIAL INTERFACE
- SERIAL REGISTER MAP
- SUMMARY OF FEATURES
- DESCRIPTION OF SERIAL REGISTERS
- THEORY OF OPERATION
- APPLICATION INFORMATION
- REVISION HISTORY

VREFT=1.5V+
V
CM
1.5V
VREFB=1.5V -
V
CM
1.5V
REFT REFB
I
SET
0.1 Fm 2.2 Fm
56.2kW
2.2 Fm 0.1 Fm
AFE5805
+ +
AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010
www.ti.com
REFERENCE CIRCUIT The device also supports the use of external
reference voltages. There are two methods to force
The digital beam-forming algorithm in an ultrasound
the references externally. The first method involves
system relies on gain matching across all receiver
pulling INT/EXT low and forcing externally REFT and
channels. A typical system would have about 12 octal
REFB to 2.5V and 0.5V nominally, respectively. In
AFEs on the board. In such a case, it is critical to
this mode, the internal reference buffer goes to a
ensure that the gain is matched, essentially requiring
3-state output. The external reference driving circuit
the reference voltages seen by all the AFEs to be the
should be designed to provide the required switching
same. Matching references within the eight channels
current for the eight ADCs inside the AFE5805. It
of a chip is done by using a single internal reference
should be noted that in this mode, CM and ISET
voltage buffer. Trimming the reference voltages on
continue to be generated from the internal bandgap
each chip during production ensures that the
voltage, as in the internal reference mode. It is
reference voltages are well-matched across different
therefore important to ensure that the common-mode
chips.
voltage of the externally-forced reference voltages
matches to within 50mV of V
CM
.
All bias currents required for the internal operation of
the device are set using an external resistor to
The second method of forcing the reference voltages
ground at the ISET pin. Using a 56kΩ resistor on
externally can be accessed by pulling INT/EXT low,
ISET generates an internal reference current of 20mA.
and programming the serial interface to drive the
This current is mirrored internally to generate the bias
external reference mode through the CM pin (register
current for the internal blocks. Using a larger external
bit called EXT_REF_VCM). In this mode, CM
resistor at ISET reduces the reference bias current
becomes configured as an input pin that can be
and thereby scales down the device operating power.
driven from external circuitry. The internal reference
However, it is recommended that the external resistor
buffers driving REFT and REFB are active in this
be within 10% of the specified value of 56kΩ so that
mode. Forcing 1.5V on the CM pin in the mode
the internal bias margins for the various blocks are
results in REFT and REFB coming to 2.5V and 0.5V,
proper.
respectively. In general, the voltages on REFT and
REFB in this mode are given by Equation 3 and
Buffering the internal bandgap voltage also generates
Equation 4:
the common-mode voltage V
CM
, which is set to the
midlevel of REFT and REFB. It is meant as a
reference voltage to derive the input common-mode if
(3)
the input is directly coupled. It can also be used to
derive the reference common-mode voltage in the
external reference mode. Figure 58 shows the (4)
suggested decoupling for the reference pins.
The state of the reference voltage internal buffers
during various combinations of the ADS_PD,
INT/EXT, and EXT_REF_VCM register bits is
described in Table 18.
Figure 58. Suggested Decoupling on the Reference Pins
46 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): AFE5805