Datasheet

5kW 5kW
CM
CLKP
CLKM
V
CM
CLKP
CLKM
DifferentialSine-Wave,
PECL,orLVDSClockInput
0.1 Fm
0.1 Fm
CLKP
CLKM
CMOSSingle-Ended
Clock
0V
CLKP
CLKM
CMOSClockInput
0.1 Fm
0.1 Fm
AFE5805
www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010
CLOCK INPUT
The eight channels on the device operate from a
single clock input. To ensure that the aperture delay
and jitter are the same for all channels, the AFE5805
uses a clock tree network to generate individual
sampling clocks to each channel. The clock paths for
all the channels are matched from the source point to
the sampling circuit. This architecture ensures that
the performance and timing for all channels are
identical. The use of the clock tree for matching
introduces an aperture delay that is defined as the
delay between the rising edge of FCLK and the actual
instant of sampling. The aperture delays for all the
channels are matched to the best possible extent. A
mismatch of ±20ps (±3s) could exist between the
aperture instants of the eight ADCs within the same
Figure 55. Internal Clock Buffer
chip. However, the aperture delays of ADCs across
two different chips can be several hundred
picoseconds apart.
The AFE5805 can operate either in CMOS
single-ended clock mode (default is DIFF_CLK = 0)
or differential clock mode (SINE, LVPECL, or LVDS).
In the single-ended clock mode, CLKM must be
forced to 0V
DC
, and the single-ended CMOS applied
on the CLKP pin. Figure 54 shows this operation.
Figure 56. Differential Clock Driving Circuit
(DIFF_CLK = 1)
Figure 54. Single-Ended Clock Driving Circuit
(DIFF_CLK = 0)
When configured for the differential clock mode
(register bit DIFF_CLK = 1) the AFE5805 clock inputs
Figure 57. Single-Ended Clock Driving Circuit
can be driven differentially (SINE, LVPECL, or LVDS)
When DIFF_CLK = 1
with little or no difference in performance between
them, or with a single-ended (LVCMOS). The
For best performance, the clock inputs must be
common-mode voltage of the clock inputs is set to
driven differentially, reducing susceptibility to
V
CM
using internal 5kΩ resistors, as shown in
common-mode noise. For high input frequency
Figure 55. This method allows using
sampling, it is recommended to use a clock source
transformer-coupled drive circuits for a sine wave
with very low jitter. Bandpass filtering of the clock
clock or ac-coupling for LVPECL and LVDS clock
source can help reduce the effect of jitter. If the duty
sources, as shown in Figure 56 and Figure 57. When
cycle deviates from 50% by more than 2% or 3%, it is
operating in the differential clock mode, the
recommended to enable the DCC through register bit
single-ended CMOS clock can be ac-coupled to the
EN_DCC.
CLKP input, with CLKM connected to ground with a
0.1mF capacitor, as Figure 57 shows.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Link(s): AFE5805