Datasheet

A1
A2
To
Attenuator
8kW
8kW
7pF0.1mF
C
IN
³ m0.1 F
V
B
(+2.4V)
IN
V
BL
T/R
AFE5805
AFE5805
www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010
APPLICATION INFORMATION
The LNA closed-loop architecture is internally
ANALOG INPUT AND LNA
compensated for maximum stability without the need
of external compensation components (inductors or
While the LNA is designed as a fully differential
capacitors). At the same time, the total input
amplifier, it is optimized to perform a single-ended
capacitance is kept to a minimum with only 16pF.
input to differential output conversion. A simplified
This architecture minimizes any loading of the signal
schematic of an LNA channel is shown in Figure 50.
source that may otherwise lead to a
A bias voltage (V
B
) of +2.4V is internally applied to
frequency-dependent voltage divider. Moreover, the
the LNA inputs through 8kΩ resistors. In addition, the
closed-loop design yields very low offsets and offset
dedicated signal input (IN pin) includes a pair of
drift; this consideration is important because the LNA
back-to-back diodes that provide a coarse input
directly drives the subsequent voltage-controlled
clamping function in case the input signal rises to
attenuator.
very large levels, exceeding 0.7V
PP
. This
configuration prevents the LNA from being driven into
The LNA of the AFE5805 uses the benefits of a
a severe overload state, which may otherwise cause
bipolar process technology to achieve an
an extended overload recovery time. The integrated
exceptionally low-noise voltage of 0.7nV/√Hz, and a
diodes are designed to handle a dc current of up to
low current noise of only 3pA/√Hz. With these
approximately 5mA. Depending on the application
input-referred noise specifications, the AFE5805
requirements, the system overload characteristics
achieves very low noise figure numbers over a wide
may be improved by adding external Schottky diodes
range of source resistances and frequencies (see
at the LNA input, as shown in Figure 50.
Figure 16, Noise Figure vs Frequency vs R
S
in the
Typical Characteristics). The optimal noise power
As Figure 50 also shows, the complementary LNA
matching is achieved for source impedances of
input (V
BL
pin) is internally decoupled by a small
around 200Ω. Further details of the AFE5805 input
capacitor. Furthermore, for each input channel, a
noise performance are shown in the Typical
separate V
BL
pin is brought out for external
Characteristic graphs.
bypassing. This bypassing should be done with a
small, 0.1mF (typical) ceramic capacitor placed in
Table 16. Noise Figure versus Source Resistance
close proximity to each V
BL
pin. Attention should be
(R
S
) at 2MHz
given to provide a low-noise analog ground for this
bypass capacitor. A noisy ground potential may
R
S
(Ω) NOISE FIGURE (dB)
cause noise to be picked up and injected into the
50 2.6
signal path, leading to higher noise levels.
200 1.0
400 1.1
1000 2.3
Figure 50. LNA Channel (Simplified Schematic)
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