Datasheet

A1
R
G
A2
Clamp
Gain
Control
Bits
From
Attenuator
Clamp
Control
Bit
To
Low-Pass
Filter
PGA
VCM
(+1.65V)
ToADC
Inputs
AFE5805
www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010
PROGRAMMABLE POST-GAIN AMPLIFIER
(PGA)
PROGRAMMABLE CLAMPING
Following the VCA is a programmable post-gain
amplifier (PGA). Figure 48 shows a simplified
To further optimize the overload recovery behavior of
schematic of the PGA, including the clamping stage.
a complete TGC channel, the AFE5805 integrates a
The gain of this PGA can be configured to four
programmable clamping stage, as shown in
different gain settings: 20dB, 25dB, 27dB, and 30dB,
Figure 49. This clamping stage precedes the
programmable through the serial port; see Table 10.
low-pass filter in order to prevent the filter circuit from
being driven into overload, the result of which would
The PGA structure consists of a differential,
be an extended recovery time. Programmable
programmable-gain voltage-to-current converter
through the serial interface, the clamping level can be
stage followed by transimpedance amplifiers to buffer
either set to clamp the signal level to approximately
each side of the differential output. Low input noise is
1.7V
PP
differential, or be disabled. Disabling the
also a requirement for the PGA design as a result of
clamp function increases the current consumption on
the large amount of signal attenuation that can be
the 3.3V analog supply (AVDD2) by about 3mA for
applied in the preceding VCA stage. At minimum
the full device. Note that with the clamp function
VCA attenuation (used for small input signals), the
enabled, the third-harmonic distortion increases.
LNA noise dominates; at maximum VCA attenuation
(large input signals), the attenuator and PGA noise
LOW-PASS FILTER
dominate.
The AFE5805 integrates an anti-aliasing filter in the
form of a programmable low-pass filter (LPF) for each
channel. The LPF is designed as a differential, active,
second-order filter that approximates a Bessel
characteristic, with typically 12dB per octave roll-off.
Figure 49 shows the simplified schematic of half the
differential active low-pass filter. Programmable
through the serial interface, the –3dB frequency
corner can be set to either 10MHz or 15MHz. The
filter bandwidth is set for all channels simultaneously.
Figure 48. Post-Gain Amplifier
(Simplified Schematic)
Figure 49. Clamping Stage and Low-Pass Filter (Simplified Schematic)
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