Datasheet

t
1
t
2
t
3
High-Level
RESET
(1.4Vto3.6V)
High-Level
CS
(1.4Vto3.6V)
DeviceReadyfor
SerialRegisterWrite
DeviceReadyfor
DataConversion
StartofClock
AVDD1
AVDD2
DVDD
AVDD 5V-
LVDD
ADS_RESET
CS
FCLK
t
4
t
7
t
8
t
6
t
5
(3.3V,5.0V)
(1.8V)
VCA_PD,ADC_PD
(2)
DeviceFully
PowersDown
DeviceFully
PowersUp
1 sm
t
(1)
WAKE
AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com
RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING
10ms < t
1
< 50ms, 10ms < t
2
< 50ms, –10ms < t
3
< 10ms, t
4
> 10ms, t
5
> 100ns, t
6
> 100ns, t
7
> 10ms, and t
8
> 100ms.
The AVDDx and LVDD power-on sequence does not matter as long as –10ms < t
3
< 10ms. Similar considerations apply while shutting down
the device.
POWER-DOWN TIMING
Power-up time shown is based on 1mF bypass capacitors on the reference pins. t
WAKE
is the time it takes for the device to wake up
completely from power-down mode. The AFE5805 has two power-down modes: complete power-down mode and partial power-down mode.
(1) t
WAKE
≤ 50ms for complete power-down mode. t
WAKE
≤ 2ms for partial power-down mode (provided the clock is not shut off during
power-down).
(2) The ADS_PD pins can be configured for partial power-down mode through a register setting.
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