Datasheet

AFE5805
www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF),
V
CNTL
= 1.0V, f
IN
= 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer
setting = 3.5mA, at ambient temperature T
A
= +25°C, unless otherwise noted.
AFE5805
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PREAMPLIFIER (LNA)
Gain A SE-input to differential output 20 dB
Input voltage V
IN
Linear operation (HD2 ≤ –40dB) 250 mV
PP
blankMaximum input voltage Limited by internal diodes 600 mV
PP
Input voltage noise (TGC) e
n
(RTI) R
S
= 0Ω, f = 1MHz 0.75 nV/√Hz
Input current noise I
n
(RTI) 3 pA/√Hz
Common-mode voltage, input V
CMI
Internally generated 2.4 V
Bandwidth BW Small-signal, –3dB 70 MHz
Input resistance
(1)
At f = 4MHz 8 kΩ
Input capacitance
(1)
Includes internal ESD and clamping diodes 16 pF
FULL-SIGNAL CHANNEL (LNA+VCA+LPF+ADC)
Input voltage noise (TGC) e
n
R
S
= 0Ω, f = 2MHz, PGA = 30dB 0.85 nV/√Hz
R
S
= 0Ω, f = 2MHz, PGA = 20dB 1.08 nV/√Hz
Noise figure NF R
S
= 200Ω, f = 5MHz 1.5 dB
Low-pass filter bandwidth LPF at –3dB, selectable through SPI 10, 15 MHz
Bandwidth tolerance ±10 %
High-pass filter HPF (First-order, due to internal ac-coupling) 200 kHz
Group delay variation ±3 ns
Overload recovery ≤ 6dB overload to within 1% 2 Clock Cycles
ACCURACY
Gain (PGA) Selectable through SPI 20, 25, 27, 30 dB
Total gain, max
(2)
LNA + PGA gain, V
CNTL
= 1.2V 48 49.5 51 dB
Gain range V
CNTL
= 0V to 1.2V 46 dB
V
CNTL
= 0.1V to 1.0V 40 dB
Gain error, absolute
(3)
0V < V
CNTL
< 0.1V ±0.5 dB
0.1V < V
CNTL
< 1.0V –1.5 ±0.5 +1.5 dB
1.0V < V
CNTL
< 1.2V ±0.5 dB
Gain matching Channel-to-channel –0.5 ±0.25 +0.5 dB
Offset error V
CNTL
= 1.0V, PGA = 30dB –39 +39 LSB
Offset error drift (tempco) ±5 ppm/°C
Clamp level CL = 0 1.7 V
PP
CL = 1 (clamp disabled) 2.8 V
PP
GAIN CONTROL (VCA)
Input voltage range V
CNTL
Gain range = 46dB 0 to 1.2 V
Gain slope V
CNTL
= 0.1V to 1.0V 44.4 dB/V
Input resistance 25 kΩ
Response time V
CNTL
= 0V to 1.2V step; to 90% signal 0.5 ms
DYNAMIC PERFORMANCE
Signal-to-noise ratio SNR f
IN
= 2MHz; –1dBFS, PGA = 30dB 59.8 dBFS
f
IN
= 5MHz; –1dBFS, PGA = 30dB 59.6 dBFS
f
IN
= 10MHz; –1dBFS, PGA = 30dB 58.8 dBFS
(1) See Figure 33.
(2) Excludes digital gain within ADC.
(3) Excludes error of internal reference.
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