Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TIMING CHARACTERISTICS
- LVDS OUTPUT TIMING CHARACTERISTICS
- LVDS OUTPUT TIMING CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- SERIAL INTERFACE
- SERIAL REGISTER MAP
- SUMMARY OF FEATURES
- DESCRIPTION OF SERIAL REGISTERS
- THEORY OF OPERATION
- APPLICATION INFORMATION
- REVISION HISTORY

Channel1
Input
V/I
Converter
VCA_SDATA
CW0
CW1
CW2
CW3
CW4
CW5
CW6
CW7
CW8
CW9
AVDD_5V
VCA_SCLK
Decode
Logic
(ToOtherChannels)
AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010
www.ti.com
Table 12. CW Switch Matrix Control for Each Channel
DBn:4 (MSB) DBn:3 DBn:2 DBn:1 (LSB) LNA INPUT CHANNEL n DIRECTED TO
0 0 0 0 Output CW0
0 0 0 1 Output CW1
0 0 1 0 Output CW2
0 0 1 1 Output CW3
0 1 0 0 Output CW4
0 1 0 1 Output CW5
0 1 1 0 Output CW6
0 1 1 1 Output CW7
1 0 0 0 Output CW8
1 0 0 1 Output CW9
1 0 1 0 Connected to AVDD_5V
1 0 1 1 Connected to AVDD_5V
1 1 0 0 Connected to AVDD_5V
1 1 0 1 Connected to AVDD_5V
1 1 1 0 Connected to AVDD_5V
1 1 1 1 Connected to AVDD_5V
Figure 42. Basic CW Cross-Point Switch Matrix Configuration
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