Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS
- DIGITAL CHARACTERISTICS
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TIMING CHARACTERISTICS
- LVDS OUTPUT TIMING CHARACTERISTICS
- LVDS OUTPUT TIMING CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- SERIAL INTERFACE
- SERIAL REGISTER MAP
- SUMMARY OF FEATURES
- DESCRIPTION OF SERIAL REGISTERS
- THEORY OF OPERATION
- APPLICATION INFORMATION
- REVISION HISTORY

AFE5805
www.ti.com
SBOS421D –MARCH 2008–REVISED MARCH 2010
Table 8. Byte 4—Third Data Byte
BIT NUMBER BIT NAME DESCRIPTION
D24 (LSB) DB5:1 Channel 5, LSB of matrix control
D25 DB5:2 Channel 5, matrix control
D26 DB5:3 Channel 5, matrix control
D27 DB5:4 Channel 5, MSB of matrix control
D28 DB6:1 Channel 6, LSB of matrix control
D29 DB6:2 Channel 6, matrix control
D30 DB6:3 Channel 6, matrix control
D31 (MSB) DB6:4 Channel 6, MSB of matrix control
Table 9. Byte 5—Fourth Data Byte
BIT NUMBER BIT NAME DESCRIPTION
D32 (LSB) DB7:1 Channel 7, LSB of matrix control
D33 DB7:2 Channel 7, matrix control
D34 DB7:3 Channel 7, matrix control
D35 DB7:4 Channel 7, MSB of matrix control
D36 DB8:1 Channel 8, LSB of matrix control
D37 DB8:2 Channel 8, matrix control
D38 DB8:3 Channel 8, matrix control
D39 (MSB) DB8:4 Channel 8, MSB of matrix control
Table 10. Clamp Level and LPF Bandwidth Setting
FUNCTION
BW D3 = 0 Bandwidth set to 15MHz (default)
BW D3 = 1 Bandwidth set to 10MHz
CL D4 = 0 Clamps the output signal at approximately –1.4dB below the full-scale of 2V
PP
.
CL D4 = 1 Clamp transparent (disabled)
Table 11. PGA Gain Setting
PG1 (D7) PG0 (D6) FUNCTION
0 0 Sets PGA gain to 20dB (default)
0 1 Sets PGA gain to 25dB
1 0 Sets PGA gain to 27dB
1 1 Sets PGA gain to 30dB
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