Datasheet

AFE5805
www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010
DESCRIPTION OF SERIAL REGISTERS
SOFTWARE RESET
ADDRESS
IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME
00 X S_RST
Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears
to '0'.
Table 3. VCA Register Information
ADDRESS
IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RES_V
03 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CA
VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA 1
(1)
1
(1)
16
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA
17
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16
VCA VCA VCA VCA VCA VCA VCA VCA
18
D39 D38 D37 D36 D35 D34 D33 D32
(1) Bits D0 and D1 of register 16 are forced to '1'.
space
• VCA_SCLK and VCA_SDATA become active only when one of the registers 16, 17, or 18 of the AFE5805
are written into.
• The contents of all three registers (total 40 bits) are written on VCA_SDATA even if only one of the above
registers is written into. This condition is only valid if the content of the register has changed because of the
most recent write. Writing contents that are the same as existing contents does not trigger activity on
VCA_SDATA.
• For example, if register 17 is written into after a RESET is applied, then the contents of register 17 as well as
the default values of the bits in registers 16 and 18 are written into VCA_SDATA.
• If register 16 is then written to, then the new contents of register 16, the previously written contents of register
17, and the default contents of register 18 are written into VCA_SDATA. Note that regardless of what is
written into D0 and D1 of register 16, the respective outputs on VCA_SDATA are always ‘1’.
• Alternatively, all three registers (16, 17 and 18) can also be written within one write cycle of the serial
interface. In that case, there would be 48 consecutive SCLK edges within the same CS active window.
• VCA_SCLK is generated using an oscillator (running at approximately 6MHz) inside the AFE5805, but the
oscillator is gated so that it is active only during the write operation of the 40 VCA bits.
• To ensure the SDATA transfer reliability, a ≥ 1ms gap is recommended between programming two VCA
registers consecutively.
VCA Reset
• VCA_CS should be permanently connected to the RST-input.
• When VCA_CS goes high (either because of an active low pulse on ADS_RESET for more than 10ns or as a
result or setting bit RES_VCA), the following functions are performed inside the AFE5805:
– Bits D0 and D1 of register 16 are forced to ‘1’
– All other bits in registers 16, 17 and 18 are RESET to the respective default values (‘0’ for all bits except
D5 of register 16 which is set to a default of ‘1’).
– No activity on signals VCA_SCLK and VCA_SDATA.
• If bit RES_VCA has been set to ‘1’, then the state machine is in the RESET state until RES_VCA is set to ‘0’.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): AFE5805