Datasheet

D15
D14
D13
D12 D11
D10 D9
D8
D7
D6 D5
D4
D3
D2 D1
D0
A7
A6 A5
A4
A3
A2 A1
A0
CS
SCLK
SDATA
DatalatchedonrisingedgeofSCLK
StartSequence EndSequence
t
6
t
4
t
2
t
7
t
3
t
5
t
1
D0 D39
VCA_SDATA
VCA_SCLK
AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com
SERIAL INTERFACE TIMING
AFE5805
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
1
SCLK period 50 ns
t
2
SCLK high time 20 ns
t
3
SCLK low time 20 ns
t
4
Data setup time 5 ns
t
5
Data hold time 5 ns
t
6
CS fall to SCLK rise 8 ns
t
7
Time between last SCLK rising edge to CS rising edge 8 ns
Internally-Generated VCA Control Signals
VCA_SCLK and VCA_SDATA signals are generated if:
• Registers with address 16, 17, or 18 (Hex) are written into, and
• EN_SM pin is HIGH
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