Datasheet

1.0
0.5
0
-
-
0.5
1.0
SamplePoints
0
80
Output( Full-Scale)±
302010 40
V =0.5V (+6dBFS)
PGA=30dB
V =1.0V
IN PP
CNTL
50 60 70 90 100 110 120
1.0
0.5
0
0.5
1.0
-
-
Time( s)m
0
15
Output( Full-Scale)±
5 10
PGA=30dB
V =1.0V
V =250mV ,0.25mV
CNTL
IN PP PP
1.0
0.5
0
-
-
0.5
1.0
Time( s)m
0
10
Output( Full-Scale)±
5
PGA=30dB
V =0Vto1.2V
CNTL
15
V
CNTL
1.0
0.5
0
-
-
0.5
1.0
Time( s)m
0
20
Output( Full-Scale)±
10
PGA=30dB
V =0.4V
CNTL
305 15 25
PD
170
150
130
110
90
70
50
30
ClockFrequency(MSPS)
5
55352515 45
I
LVDD
I
AVDD1
ZeroInputonAllChannels
I ,I (mA)
AVDD1 LVDD
995
990
985
980
975
970
965
960
955
950
945
Temperature( C)°
-40
85
TotalPower(mW)
0 25
TGCMode
50 70
AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com
TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF,
V
CNTL
= 1.0V, f
IN
= 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature T
A
= +25°C, unless otherwise noted.
FULL CHANNEL OVERLOAD OVERLOAD RECOVERY
Figure 35. Figure 36.
V
CNTL
RESPONSE TIME POWER-UP/POWER-DOWN RESPONSE TIME
Figure 37. Figure 38.
AVDD1 AND LVDD POWER-SUPPLY CURRENTS
vs CLOCK FREQUENCY POWER DISSIPATION vs TEMPERATURE
Figure 39. Figure 40.
20 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): AFE5805