Datasheet

AFE5805
www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010
LVDS OUTPUT TIMING CHARACTERISTICS
(1) (2)
Typical values are at +25°C, minimum and maximum values over specified temperature range of T
MIN
= 0°C to T
MAX
= +70°C, sampling
frequency = as specified, C
LOAD
= 5pF
(3)
, I
OUT
= 3.5mA, R
LOAD
= 100Ω
(4)
, and no internal termination, unless otherwise noted.
AFE5805
40MSPS 50MSPS
PARAMETER TEST CONDITIONS
(5)
MIN TYP MAX MIN TYP MAX UNIT
t
SU
Data setup time
(6)
Data valid
(7)
to zero-crossing of LCLKP 0.67 0.47 ns
Zero-crossing of LCLKP to data becoming
t
H
Data hold time
(6)
0.85 0.65 ns
invalid
(7)
ADC input clock rising edge cross-over to
t
PROP
Clock propagation delay 10 14 16.6 10 12.5 14.1 ns
output clock (FCLKP) rising edge cross-over
Duty cycle of differential clock,
LVDS bit clock duty cycle 45.5 50 53 45 50 53.5
(LCLKP – LCLKM)
Bit clock cycle-to-cycle jitter 250 250 ps, pp
Frame clock cycle-to-cycle jitter 150 150 ps, pp
Rise time is from –100mV to +100mV
t
RISE
, t
FALL
Data rise time, data fall time 0.09 0.2 0.4 0.09 0.2 0.4 ns
Fall time is from +100mV to –100mV
t
CLKRISE
, Output clock rise time, output Rise time is from –100mV to +100mV
0.09 0.2 0.4 0.09 0.2 0.4 ns
t
CLKFALL
clock fall time Fall time is from +100mV to –100mV
(1) All characteristics are at the maximum rated speed for each speed grade.
(2) Timing parameters are ensured by design and characterization; not production tested.
(3) C
LOAD
is the effective external single-ended load capacitance between each output pin and ground.
(4) I
OUT
refers to the LVDS buffer current setting; R
LOAD
is the differential load resistance between the LVDS output pair.
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.
LVDS OUTPUT TIMING CHARACTERISTICS
(1) (2)
Typical values are at +25°C, minimum and maximum values over specified temperature range of T
MIN
= 0°C to T
MAX
= +70°C, sampling
frequency = as specified, C
LOAD
= 5pF
(3)
, I
OUT
= 3.5mA, R
LOAD
= 100Ω
(4)
, and no internal termination, unless otherwise noted.
AFE5805
30MSPS 20MSPS 10MSPS
PARAMETER TEST CONDITIONS
(5)
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT
Data valid
(7)
to zero-crossing of
t
SU
Data setup time
(6)
0.8 1.5 3.7 ns
LCLKP
Zero-crossing of LCLKP to data
t
H
Data hold time
(6)
1.2 1.9 3.9 ns
becoming invalid
(7)
ADC input clock rising edge
t
PROP
Clock propagation delay cross-over to output clock (FCLKP) 9.5 13.5 17.3 9.5 14.5 17.3 10 14.7 17.1 ns
rising edge cross-over
Duty cycle of differential clock,
LVDS bit clock duty cycle 46.5 50 52 48 50 51 49 50 51
(LCLKP – LCLKM)
Bit clock cycle-to-cycle
250 250 750 ps, pp
jitter
Frame clock cycle-to-cycle
150 150 500 ps, pp
jitter
t
RISE
, Data rise time, data fall Rise time is from –100mV to +100mV
0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns
t
FALL
time Fall time is from +100mV to –100mV
t
CLKRISE
, Output clock rise time, Rise time is from –100mV to +100mV
0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns
t
CLKFALL
output clock fall time Fall time is from +100mV to –100mV
(1) All characteristics are at the speeds other than the maximum rated speed for each speed grade.
(2) Timing parameters are ensured by design and characterization; not production tested.
(3) C
LOAD
is the effective external single-ended load capacitance between each output pin and ground.
(4) I
OUT
refers to the LVDS buffer current setting; R
LOAD
is the differential load resistance between the LVDS output pair.
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.
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