Datasheet

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
Sample n
Sample n+12
t
PROP
t (A)
D
12clockslatency
ADC
Input
(1)
Clock
Input
6XFCLK
LCLKM
LCLKP
1XFCLK
FCLKM
FCLKP
SERIAL DATA
OUTP
OUTM
t
SAMPLE
Sample n+13
t
H1
t
SU1
t
H2
t
SU2
LCLKM
LCLKP
OUTM
OUTP
t =min(t ,t )
t =min(t ,t )
SU SU1 SU2
H H1 H2
AFE5805
SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com
LVDS TIMING DIAGRAM
(1) Referenced to ADC Input (internal node) for illustration purposes only.
DEFINITION OF SETUP AND HOLD TIMES
TIMING CHARACTERISTICS
(1)
AFE5805
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
D(A)
ADC aperture delay 1.5 4.5 ns
Aperture delay variation Channel-to-channel within the same device (3s) ±20 ps
t
J
Aperture jitter 400 f
S
, rms
Time to valid data after coming out of
50 ms
COMPLETE POWER-DOWN mode
Time to valid data after coming out of PARTIAL
t
WAKE
Wake-up time POWER-DOWN mode (with clock continuing to 2 ms
run during power-down)
Time to valid data after stopping and restarting
40 ms
the input clock
Clock
Data latency 12
cycles
(1) Timing parameters are ensured by design and characterization; not production tested.
12 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): AFE5805