Datasheet

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Table Of Contents

LNA8Channels

SPI

IN1

IN8

CH1

LVDS

OUT

CH8

VCA/PGA

Clamp

and

LPF

Logic/Controls

Reference

CWSwitchMatrix(8 10)´

I (10)

OUT

12-Bit

ADC

AFE5805

www.ti.com

SBOS421D –MARCH 2008–REVISED MARCH 2010

FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND

0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel

Check for Samples: AFE5805

FEATURES

DESCRIPTION

• 8-Channel Complete Analog Front-End:

The AFE5805 is a complete analog front-end device

specifically designed for ultrasound systems that

– LNA, VCA, PGA, LPF, and ADC

require low power and small size.

• Ultra-Low, Full-Channel Noise:

The AFE5805 consists of eight channels, including a

– 0.85nV/√Hz (TGC)

low-noise amplifier (LNA), voltage-controlled

– 1.1nV/√Hz (CW)

attenuator (VCA), programmable gain amplifier

• Low Power:

(PGA), low-pass filter (LPF), and a 12-bit

analog-to-digital converter (ADC) with low voltage

– 122mW/Channel (40MSPS)

differential signaling (LVDS) data outputs.

– 74mW/Channel (CW Mode)

The LNA gain is set for 20dB gain, and has excellent

• Low-Noise Pre-Amp (LNA):

noise and signal handling capabilities, including fast

– 0.75nV/√Hz

overload recovery. VCA gain can vary over a 46dB

– 20dB Fixed Gain

range with a 0V to 1.2V control voltage common to all

channels of the AFE5805.

– 250mV

Linear Input Range

• Variable-Gain Amplifier:

The PGA can be programmed for gains of 20dB,

25dB, 27dB, and 30dB. The internal low-pass filter

– Gain Control Range: 46dB

can also be programmed to 10MHz or 15MHz.

• PGA Gain Settings: 20dB, 25dB, 27dB, 30dB

The LVDS outputs of the ADC reduce the number of

• Low-Pass Filter:

interface lines to an ASIC or FPGA, thereby enabling

– Selectable BW: 10MHz, 15MHz

the high system integration densities desired for

– 2nd-Order

portable systems. The ADC can either be operated

with internal or external references. The ADC also

• Gain Error: ±0.5dB

features a signal-to-noise ratio (SNR) enhancement

• Channel Matching: ±0.25dB

mode that can be useful at high gains.

• Distortion, HD2: –65dBFS at 5MHz

The AFE5805 is available in a 15mm × 9mm,

• Clamping Control

135-ball BGA package that is Pb-free

• Fast Overload Recovery: Two Clock Cycles

(RoHS-compliant) and green. It is specified for

operation from 0°C to +70°C.

• 12-Bit Analog-to-Digital Converter:

– 10MSPS to 50MSPS

– 69.5dB SNR at 10MHz

– Serial LVDS Interface

• Integrated CW Switch Matrix

• 15mm × 9mm, 135-BGA Package:

– Pb-Free (RoHS-Compliant) and Green

APPLICATIONS

• Medical Imaging, Ultrasound

– Portable Systems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Infineon is a registered trademark of Infineon Technologies.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (52 pages)

PAGE 1
AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel Check for Samples: AFE5805 FEATURES DESCRIPTION • The AFE5805 is a complete analog front-end device specifically designed for ultrasound systems that require low power and small size. 1 23 • • • • • • • • • • • • • • 8-Channel Complete Analog Front-End: – LNA, VCA, PGA, LPF, and ADC Ultra-Low, Full-Channel Noise: – 0.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF), VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF), VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0mF), VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted. AFE5805 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD1, AVDD2, DVDD Operating 3.15 3.3 3.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com DIGITAL CHARACTERISTICS DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level '0' or '1'. At CLOAD = 5pF (1), IOUT = 3.5mA (2), RLOAD = 100Ω (2), and no internal termination, unless otherwise noted. AFE5805 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V DIGITAL INPUTS High-level input voltage 1.4 3.3 Low-level input voltage 0 0.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 AFE5805 LVDD (1.8V) AVDD1 (3.3V) CLKM CLKP AVDD2 (3.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.
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AFE5805 www.ti.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com Table 1. TERMINAL FUNCTIONS PIN NO. PIN NAME FUNCTION H7 CS Input Chip select for serial interface; active low H1 ADS_PD Input Power-down pin for ADS; active high. See the Power-Down Modes section for more information.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 Table 1. TERMINAL FUNCTIONS (continued) PIN NO.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com LVDS TIMING DIAGRAM Sample n Sample n + 12 ADC Input tD(A) (1) Sample n + 13 Clock Input tSAMPLE 12 clocks latency LCLKM 6X FCLK LCLKP OUTP SERIAL DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 OUTM FCLKM 1X FCLK FCLKP tPROP (1) Referenced to ADC Input (internal node) for illustration purposes only.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 LVDS OUTPUT TIMING CHARACTERISTICS (1) (2) Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +70°C, sampling frequency = as specified, CLOAD = 5pF (3), IOUT = 3.5mA, RLOAD = 100Ω (4), and no internal termination, unless otherwise noted. AFE5805 40MSPS 50MSPS PARAMETER TEST CONDITIONS (5) MIN tSU Data setup time (6) Data valid (7) to zero-crossing of LCLKP 0.67 0.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF, VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF, VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted. GAIN MATCH AT VCNTL = 1.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF, VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF, VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted. CW INPUT-REFERRED NOISE vs FREQUENCY CW ACCURACY 1.30 4000 1.28 3500 3000 1.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF, VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF, VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1mF, VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted. OVERLOAD RECOVERY 1.0 0.5 0.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 SERIAL INTERFACE The AFE5805 has a set of internal registers that can be accessed through the serial interface formed by pins CS (chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data).
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 SERIAL REGISTER MAP Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 00 (2) (3) (4) D0 NAME DESCRIPTION X S_RST Self-clearing software RESET.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) (2) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 X D6 X D5 D4 X (3) (4) (continued) D3 D2 D1 D0 NAME X X X X GAIN_CH4<3:0> Programmable gain channel 4. 0dB gain GAIN_CH3<3:0> Programmable gain channel 3. 0dB gain GAIN_CH2<3:0> Programmable gain channel 2.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 DESCRIPTION OF SERIAL REGISTERS SOFTWARE RESET ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X S_RST 00 Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears to '0'. Table 3.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com INPUT REGISTER BIT MAPS Table 4. VCA Register Map BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 D0:D7 D8:D11 D12:D15 D16:D19 D20:D23 D24:D27 D28:D31 D32:D35 D36:D39 Control CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 Table 5.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 Table 8. Byte 4—Third Data Byte BIT NUMBER BIT NAME DESCRIPTION D24 (LSB) DB5:1 Channel 5, LSB of matrix control D25 DB5:2 Channel 5, matrix control D26 DB5:3 Channel 5, matrix control D27 DB5:4 Channel 5, MSB of matrix control D28 DB6:1 Channel 6, LSB of matrix control D29 DB6:2 Channel 6, matrix control D30 DB6:3 Channel 6, matrix control D31 (MSB) DB6:4 Channel 6, MSB of matrix control Table 9.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com Table 12.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 POWER-DOWN MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 X 0F D6 X D5 X D4 D3 D2 D1 D0 NAME X X X X PDN_CH<1:4> X PDN_CH<8:5> X PDN_PARTIAL 0 X PDN_COMPLETE X 0 PDN_PIN_CFG Each of the eight ADC channels within the AFE5805 can be individually powered down. PDN_CH controls the power-down mode for the ADC channel .
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com Table 13. Bit Clock Drive Strength (1) (1) ILVDS_LCLK<2> ILVDS_LCLK<1> ILVDS_LCLK<0> LVDS DRIVE STRENGTH FOR LCLKP AND LCLKM 0 0 0 3.5mA (default) 0 0 1 2.5mA 0 1 0 1.5mA 0 1 1 0.5mA 1 0 0 7.5mA 1 0 1 6.5mA 1 1 0 5.5mA 1 1 1 4.5mA Current settings lower than 1.5mA are not recommended.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 LOW-FREQUENCY NOISE SUPPRESSION MODE ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X LFNS_CH<1:4> 14 X X X X LFNS_CH<8:5> The low-frequency noise suppression mode is especially useful in applications where good noise performance is desired in the frequency band of 0MHz to 1MHz (around dc).
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com PROGRAMMABLE GAIN ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 X D6 X D5 D4 X D3 D2 D1 D0 NAME X X X X GAIN_CH4<3:0> X GAIN_CH3<3:0> 2A X X X X X X X X X X X X GAIN_CH2<3:0> GAIN_CH1<3:0> GAIN_CH5<3:0> X X X X GAIN_CH6<3:0> 2B X X X X GAIN_CH7<3:0> X X X X GAIN_CH8<3:0> The AFE5805, through its registers, allows for a digital gain to be programmed for each channel.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 CLOCK, REFERENCE, AND DATA OUTPUT MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 1 1 1 1 1 1 D6 D5 D4 D3 D2 X D1 D0 NAME X DIFF_CLK EN_DCC 42 1 1 1 1 1 1 X X EXT_REF_VCM X PHASE_DDR<1:0> X X BTC_MODE MSB_FIRST 46 1 1 1 1 X EN_SDR 1 1 FALL_SDR INPUT CLOCK The AFE5805 is configured by default to operate with a single-ended input clock; CLKP is driven by a CMOS clock and CLKM is tied to '0'.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com BIT CLOCK PROGRAMMABILITY The output interface of the AFE5805 is normally a DDR interface, with the LCLK rising edge and falling edge transitions in the middle of alternate data windows. Figure 43 shows this default phase. FCLKP LCLKP OUTP Figure 43. LCLK Default Phase The phase of LCLK can be programmed relative to the output frame clock and data using bits PHASE_DDR<1:0>. Figure 44 shows the LCLK phase modes.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12 times the input clock, or twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two manners shown in Figure 45.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING t1 (3.3V, 5.0V) AVDD1 AVDD2 DVDD AVDD-5V LVDD t2 (1.8V) t3 t4 t7 High-Level RESET (1.4V to 3.6V) t5 ADS_RESET t6 Device Ready for Serial Register Write High-Level CS (1.4V to 3.6V) CS Start of Clock Device Ready for Data Conversion FCLK t8 10ms < t1 < 50ms, 10ms < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100ms.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 THEORY OF OPERATION The AFE5805 is an 8-channel, fully integrated analog front-end device controlling the LNA, attenuator, PGA, LPF, and ADC, that implements a number of proprietary circuit design techniques to specifically address the performance demands of medical ultrasound systems. It offers unparalleled low-noise and low-power performance at a high level of integration.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com LOW-NOISE AMPLIFIER (LNA) As with many high-gain systems, the front-end amplifier is critical to achieve a certain overall performance level. Using a new proprietary architecture, the LNA of the AFE5805 delivers exceptional low-noise performance, while operating on a very low quiescent current compared to CMOS-based architectures with similar noise performances.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 PROGRAMMABLE POST-GAIN AMPLIFIER (PGA) Following the VCA is a programmable post-gain amplifier (PGA). Figure 48 shows a simplified schematic of the PGA, including the clamping stage. The gain of this PGA can be configured to four different gain settings: 20dB, 25dB, 27dB, and 30dB, programmable through the serial port; see Table 10.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com ANALOG-TO-DIGITAL CONVERSION The analog-to-digital converter (ADC) of the AFE5805 employs a pipelined converter architecture that consists of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 12-bit level.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 APPLICATION INFORMATION The LNA closed-loop architecture is internally compensated for maximum stability without the need of external compensation components (inductors or capacitors). At the same time, the total input capacitance is kept to a minimum with only 16pF. This architecture minimizes any loading of the signal source that may otherwise lead to a frequency-dependent voltage divider.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com OVERLOAD RECOVERY ±0.3V can significantly reduce the overall overload recovery performance. The T/R switch characteristics are largely determined by the biasing current of the diodes, which can be set by adjusting the 3kΩ resistor values; for example, setting a higher current level may lead to an improved switching characteristic and reduced noise contribution.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 VCA—GAIN CONTROL The attenuator (VCA) for each of the eight channels of the AFE5805 is controlled by a single-ended control signal input, the VCNTL pin. The control voltage range spans from 0V to 1.2V, referenced to ground. This control voltage varies the attenuation of the VCA based on its linear-in-dB characteristic with its maximum attenuation (minimum gain) at VCNTL = 0V, and minimum attenuation (maximum gain) at VCNTL = 1.2V.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com The resulting signal current then passes through the 8×10 switch matrix. Depending on the programmed configuration of the switch matrix, any V/I amplifier current output can be connected to any of 10 CW outputs. This design is a simple current-summing circuit such that each CW output can represent the sum of any or all of the channel currents.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 CLOCK INPUT The eight channels on the device operate from a single clock input. To ensure that the aperture delay and jitter are the same for all channels, the AFE5805 uses a clock tree network to generate individual sampling clocks to each channel. The clock paths for all the channels are matched from the source point to the sampling circuit. This architecture ensures that the performance and timing for all channels are identical.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com REFERENCE CIRCUIT The device also supports the use of external reference voltages. There are two methods to force the references externally. The first method involves pulling INT/EXT low and forcing externally REFT and REFB to 2.5V and 0.5V nominally, respectively. In this mode, the internal reference buffer goes to a 3-state output.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 Table 18. State of Reference Voltages for Various Combinations of ADS_PD and INT/EXT PIN, REGISTER BIT (1) INTERNAL BUFFER STATE ADS_PD pin 0 0 1 1 0 0 1 1 INT/EXT pin 0 1 0 1 0 1 0 1 EXT_REF_VCM 0 0 0 0 1 1 1 1 REFT buffer 3-state 2.5V 3-state 2.5V (1) 1.5V + VCM/1.5V Do not use 2.5V (1) Do not use REFB buffer 3-state 0.5V 3-state 0.5V (1) 1.5V – VCM/1.5V Do not use 0.5V (1) Do not use CM pin 1.
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AFE5805 SBOS421D – MARCH 2008 – REVISED MARCH 2010 www.ti.com GROUNDING AND BYPASSING The AFE5805 distinguishes between three different grounds: AVSS1 and AVSS2 (analog grounds), and LVSS (digital ground). In most cases, it should be adequate to lay out the printed circuit board (PCB) to use a single ground plane for the AFE5805. Care should be taken that this ground plane is properly partitioned between various sections within the system to minimize interactions between analog and digital circuitry.
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AFE5805 www.ti.com SBOS421D – MARCH 2008 – REVISED MARCH 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October, 2008) to Revision D Page • Changed Output transconductance specification notation from V/I to IOUT/VIN ..................................................................... 4 • Changed Input clock (FCLK) rising edge to ADC input clock for Clock propagation delay parameter description ............
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PACKAGE OPTION ADDENDUM www.ti.com 15-Jan-2011 PACKAGING INFORMATION Orderable Device AFE5805ZCF Status (1) ACTIVE Package Type Package Drawing NFBGA ZCF Pins Package Qty 135 160 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish SNAGCU MSL Peak Temp (3) Samples (Requires Login) Level-3-260C-168 HR Contact TI Distributor or Sales Office (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.