Datasheet

12-Bit
ADC
PLL
Serializer
1xADCLK
6xADCLK
IN1
OUT1P
OUT1M
LCLKP
LCLKM
FCLKP
FCLKM
12xADCLK
12-Bit
ADC
Serializer
DigitalLPFPGA
Digital
Reference
REFT
INT/
EXT
CW[0:9]
REFB
CM
OUT8P
OUT8M
ISET
Registers
SDATA
CS
SCLK
ADC
Control
PD
Clock
Buffer
(ADCLK)
CLKP
AVSS2 AVDD2
(3.3V)
(AVSS)
CLKM
AVDD
(3.3V)
LVDD
(1.8V)
Power-
Down
TestP
atterns
DriveCurrent
OutputF
ormat
DigitalGain
(0dBto12dB)
¼ ¼ ¼
VCALNA
¼
IN8
VCNTL
LPFPGAVCA
CWSwitchMatrix
(8x10)
LNA
¼
¼
¼ ¼
¼
¼
Channels
2to7
ADC_
RESET
¼
¼
T
SCLK
AVDD_5V
DVDD(3.3V)
AVSS1
20,25,27
30dB
AFE5804
¼
12.5,17MHz
AFE5804
www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011
FUNCTIONAL BLOCK DIAGRAM
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