Datasheet

AFE5804
www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011
Table 20. State of Reference Voltages for Various Combinations of PD and INT/EXT
REGISTER BIT INTERNAL BUFFER STATE
PD 0 0 1 1 0 0 1 1
INT/EXT 0 1 0 1 0 1 0 1
EXT_REF_VCM 0 0 0 0 1 1 1 1
REFT buffer 3-state 2.5V 3-state 2.5V
(1)
1.5V + V
CM
/1.5V Do not use 2.5V
(1)
Do not use
REFB buffer 3-state 0.5V 3-state 0.5V
(1)
1.5V – V
CM
/1.5V Do not use 0.5V
(1)
Do not use
CM pin 1.5V 1.5V 1.5V 1.5V Force Do not use Force Do not use
(1) Weakly forced with reduced strength.
Poor RMS jitter (greater than 100ps), combined with
POWER SUPPLIES
inadequate power-supply design (for example, supply
voltage drops and ripple increases), can affect LVDS
The AFE5804 operates on three supply rails: a digital
timing. As a result, occasional glitches might be
1.8V supply, and the 3.3V and 5V analog supplies. At
observed on the AFE5804 outputs. If this
initial power-up, the part is operational in TGC mode,
phenomenon is observed, or if the clock jitter and
with the registers in the respective default
LVDD noise are concerns in the system, the registers
configurations (see Table 3).
in Table 21 can be written as part of the initialization
In TGC mode, only the VCA (attenuator) draws a low
sequence in order to stabilize LVDS clock timing and
current (typically 7mA) from the 5V supply. Switching
SNR performance.
into the CW mode, the internal V/I-amplifiers are then
powered from the 5V rail as well, raising the
Table 21. Address and Data in Hexadecimal
operating current on the 5V rail. At the same time, the
ADDRESS DATA
post-gain amplifiers (PGA) are being powered down,
01 0010h
thereby reducing the current consumption on the 3.3V
rail (refer to the Electrical Characteristics table for
D1 0140h
details on TGC mode and CW mode current
DA 0001h
consumption).
E1 0020h
All analog supply rails for the AFE5804 should be low
02 0080h
noise, including the 3.3V digital supply DVDD that
01 0000h
connects to the internal logic blocks of the VCA within
the AFE5804. It is recommended to tie the DVDD
Writing to these registers has the following additional
pins to the same 3.3V analog supply as the AVDD1/2
effects:
pins, rather than a different 3.3V rail that may also
a. Total chip power increases approximately
provide power to other logic device in the system.
8mW—this amount includes a current increase of
Transients and noise generated by those devices can
about 1.9mA on AVDD1 and about 1.1mA on
couple into the AFE5804 and degrade overall device
LVDD.
performance.
b. With reference to the LVDS Timing Diagram and
Definition of Setup and Hold Times,
CLOCK JITTER, POWER NOISE, SNR, AND
LCLKP/LCLKM shift by about 100ps to the left
LVDS TIMING
relative to CLK and OUTP/OUTM. This shift
As explained in Application Note SLYT075, ADC
causes the data setup time to reduce by 100ps
clock jitter can degrade ADC performance. Therefore,
and the data hold time to increase by 100ps.
it is always preferred to use a low jitter clock to drive
c. The clock propagation delay (t
PROP
) is reduced by
the AFE5804. To ensure the performance of the
roughly 2ns. The typical and minimum values for
AFE5804, a clock with a jitter of 1ps RMS or better is
this specification are reduced by 2ns, and the
expected. However, it might not always be possible to
maximum value for this spec is reduced by 1.5ns.
achieve this for practical reasons. With a higher clock
jitter, the SNR of the AFE5804 may be degraded as
Power-supply noise can usually be minimized if
well as the LVDS timing stability. In addition, clean
grounding, bypassing, and PCB layout are well
and stable power supplies are always preferred to
managed. Some guidelines can be found in the
maximize the AFE5804 SNR and ensure LVDS timing
Grounding and Bypassing and Board Layout
stability.
sections.
Copyright © 2008–2011, Texas Instruments Incorporated 57