Datasheet
C
IN
LNA
V/I
CWSwitchMatrix
Attenuator
(VCA)
PGA
Clamp
LPF
CW/I
OUT
OUT
OUT
T/R
Switch
V
CNTL
AFE5804
LVDS
Serializer
12-Bit
ADC
AFE5804
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SBOS442C –JUNE 2008–REVISED OCTOBER 2011
THEORY OF OPERATION
of 0V to 1.2V. While the LNA is designed to be driven
The AFE5804 is an eight-channel, fully integrated
from a single-ended source, the internal TGC signal
analog front-end device. Its integrated LNA,
path is designed to be fully differential to maximize
attenuator, PGA, LPF, and ADC implement a number
dynamic range while also optimizing for low,
of proprietary circuit design techniques to specifically
even-order harmonic distortion.
address the performance demands of medical
ultrasound systems. It offers unparalleled low-noise CW doppler signal processing is facilitated by routing
and low-power performance at a high level of the differential LNA outputs to V/I amplifier stages.
integration. For the TGC signal path, each channel The resulting signal currents of each channel then
consists of a 20dB fixed-gain low-noise amplifier connect to an 8×10 switch matrix that is controlled
(LNA), a linear-in-dB voltage-controlled attenuator through the serial interface and a corresponding
(VCA), and a programmable gain amplifier (PGA), as register. The CW outputs are typically routed to a
well as a clamping and low-pass filter stage. passive delay line that allows coherent summing
Digitally-controlled through the logic interface, the (beam forming) of the active channels and additional
PGA gain can be set to four different settings: 20dB, off-chip signal processing, as shown in Figure 97.
25dB, 27dB, and 30dB. At its highest setting, the total
Applications that do not utilize the CW path can
available gain of the AFE5804 is therefore 50dB. To
simply operate the AFE5804 in TGC mode. In this
facilitate the logarithmic time-gain compensation
mode, the CW blocks (V/I amplifiers and switch
required for ultrasound systems, the VCA is designed
matrix) remain powered down, and the CW outputs
to provide a 46dB attenuation range. Here, all
can be left unconnected.
channels are simultaneously controlled by an
externally-applied control voltage (V
CNTL
) in the range
Figure 97. Functional Block Diagram
Copyright © 2008–2011, Texas Instruments Incorporated 47