Datasheet

AFE5804

www.ti.com

SBOS442C –JUNE 2008–REVISED OCTOBER 2011

INPUT REGISTER BIT MAPS

Table 5. VCA Register Map

BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5

D0:D7 D8:D11 D12:D15 D16:D19 D20:D23 D24:D27 D28:D31 D32:D35 D36:D39

Control CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8

Table 6. Byte 1—Control Byte Register Map

BIT NUMBER BIT NAME DESCRIPTION

D0 (LSB) 1 Start bit; this bit is permanently set high = 1

D1 WR Write bit; this bit is permanently set high = 1

D2 PWR 1= Power-down mode enabled

D3 BW Low-pass filter bandwidth setting (see Table 11)

D4 M0 (see Table 12)

D5 M1 (see Table 12)

D6 PG0 LSB of PGA gain control (see Table 13)

D7 (MSB) PG1 MSB of PGA gain control

Table 7. Byte 2—First Data Byte

BIT NUMBER BIT NAME DESCRIPTION

D8 (LSB) DB1:1 Channel 1, LSB of matrix control

D9 DB1:2 Channel 1, matrix control

D10 DB1:3 Channel 1, matrix control

D11 DB1:4 Channel 1, MSB of matrix control

D12 DB2:1 Channel 2, LSB of matrix control

D13 DB2:2 Channel 2, matrix control

D14 DB2:3 Channel 2, matrix control

D15 (MSB) DB2:4 Channel 2, MSB of matrix control

Table 8. Byte 3—Second Data Byte

BIT NUMBER BIT NAME DESCRIPTION

D16 (LSB) DB3:1 Channel 3, LSB of matrix control

D17 DB3:2 Channel 3, matrix control

D18 DB3:3 Channel 3, matrix control

D19 DB3:4 Channel 3, MSB of matrix control

D20 DB4:1 Channel 4, LSB of matrix control

D21 DB4:2 Channel 4, matrix control

D22 DB4:3 Channel 4, matrix control

D23 (MSB) DB4:4 Channel 4, MSB of matrix control