Datasheet

(connect externally)
VCA_CS RST
[H4]
[H9]
VCA_SCLK
VCA_SDATA
ADS_CS
ADS_SCLK
ADS_SDATA
ADS_RESET
ADS_RESET
[H8]SDATA
[H7]CS
[H6]SCLK
[L9]
EN_SM
Tie to:
+3.3V (AVDD1)
[H5]
AFE5804
SPI Interface and Register
AFE5804
SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com
SERIAL INTERFACE
The AFE5804 has a set of internal registers that can be accessed through the serial interface formed by pins CS
(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the
following actions occur:
• Serial shift of bits into the device is enabled
• SDATA (serial data) is latched at every rising edge of SCLK
• SDATA is loaded into the register at every 24th SCLK rising edge
If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of
24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16
bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds
(a few hertz) and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the respective default values. Initialization can be
done in one of two ways:
1. Through a hardware reset, by applying a low-going pulse on the ADS_RESET pin; or
2. Through a software reset; using the serial interface, set the S_RST bit high. Setting this bit initializes the
internal registers to the respective default values and then self-resets the bit low. In this case, the
ADS_RESET pin stays high (inactive).
3. The registers in Table 2 must be programmed after the initialization stage. The power-supply ripple and clock
jitter effects can be minimized.
Table 2. Register Data
ADDRESS DATA
01 0010h
D1 0140h
DA 0001h
E1 0020h
02 0080h
01 0000h
Serial Port Interface (SPI) Information
Figure 92. Typical Connection Diagram for the SPI Control Lines
30 Copyright © 2008–2011, Texas Instruments Incorporated