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11.2 ADC Clock
Figure 8. AFE5803EVM Jumper Locations
Table 2. PGATestMode, ADC Clock
Clock Reference
Description
Type Designator
J9/J10/J12/J1 N/A
3
PGA Test
JP52/JP53/JP
Test points for PGA test mode.
56/JP57
JP9 selects on_board_ADC CMOS clock or external clock from J14. Default setup uses
onboard CMOS clock. Set it to the other side to use the external clock source.
JP9/JP10
ADC
JP10 Short to power up onboard CMOS clock.
J14 External ADC clock Input.
16
AFE5803EVM (Revision E ) Evaluation Module SLOU332A– January 2012– Revised January 2012
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