Datasheet

AFE4490
SBAS602F –DECEMBER 2012–REVISED OCTOBER 2013 www.ti.com
• Added Timing, Wake-up time from Rx power-down and Wake-up time from Tx power-down parameters to Electrical
Characteristics table ............................................................................................................................................................. 6
• Changed Supply Current section of Electrical Characteristics table .................................................................................... 7
• Changed typical specification in first row and unit in second row of Power Dissipation, P
D(q)
parameter in Electrical
Characteristics table ............................................................................................................................................................. 8
• Changed Power Dissipation, After reset LED_DRV_SUP typical specification in Electrical Characteristics table .............. 8
• Changed Power Dissipation, With stage 2 mode enabled LED_DRV_SUP, TX_CTRL_SUP, and RX_DIG_SUP
typical specifications in Electrical Characteristics table ........................................................................................................ 8
• Changed pin out figure ....................................................................................................................................................... 11
• Added Figure 11 ................................................................................................................................................................. 14
• Deleted Figure 11, INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (BW = 5 Hz, PRF = 5000 Hz) .......... 14
• Deleted Figure 17, INPUT-REFERRED NOISE CURRENT vs PLETH CURRENT (BW = 20 Hz, PRF = 5000 Hz) ........ 15
• Added Figure 22 ................................................................................................................................................................. 15
• Deleted Figure 23, NOISE-FREE BITS vs PLETH CURRENT (BW = 5 Hz, PRF = 5000 Hz) .......................................... 16
• Added Figure 22 ................................................................................................................................................................. 16
• Deleted Figure 29, NOISE-FREE BITS vs PLETH CURRENT (BW = 20 Hz, PRF = 5000 Hz) ........................................ 17
• Added Figure 36 through Figure 39 .................................................................................................................................... 18
• Added Figure 47 to Figure 51 ............................................................................................................................................. 20
• Changed gain setting range in Receiver Front-End section ............................................................................................... 23
• Changed corresponding register column description in rows t
24
, t
26
, and t
28
in Table 3 .................................................... 31
• Added text reference for Figure 63 in ADC Operation and Averaging Module section ...................................................... 34
• Changed last paragraph of AFE Analog Output Mode (ADC Bypass Mode) section ........................................................ 39
• Changed description of LED Power Reduction During Periods of Inactivity section .......................................................... 43
• Updated Figure 75 .............................................................................................................................................................. 44
• Updated Figure 76 .............................................................................................................................................................. 45
• Changed LED2CONVEND register name in Table 5 ......................................................................................................... 51
• Changed RESERVED1 and RESERVED2 register descriptions in Table 5 ...................................................................... 52
• Changed description of bits D[15:0] in LED2STC register ................................................................................................. 53
• Changed description of bits D[15:0] in LED2ENDC, LED2LEDSTC, and LED2LEDENDC registers ................................ 54
• Changed description of bits D[15:0] in ALED2STC, ALED2ENDC, and LED1STC registers ............................................ 55
• Changed description of bits D[15:0] in LED1ENDC, LED1LEDSTC, and LED1LEDENDC registers ................................ 56
• Changed description of bits D[15:0] in ALED1STC, ALED1ENDC, and LED2CONVST registers .................................... 57
• Changed LED2CONVEND register .................................................................................................................................... 58
• Changed description of bits D[15:0] in ALED2CONVST and ALED2CONVEND registers ................................................ 58
• Changed description of bits D[15:0] in LED1CONVST, LED1CONVEND, and ALED1CONVST registers ....................... 59
• Changed description of bits D[15:0] in ALED1CONVEND register .................................................................................... 60
• Changed RESET to RESET in ADCRSTSTCT0 and ADCRSTENDCT0 registers ............................................................ 60
• Changed RESET to RESET in ADCRSTSTCT1, ADCRSTENDCT1, and ADCRSTSTCT2 registers ............................... 61
• Changed RESET to RESET in ADCRSTENDCT2, ADCRSTSTCT3, and ADCRSTENDCT3 registers ............................ 62
• Added footnote to Table 7 .................................................................................................................................................. 66
• Changed bits D18 and D17 names in CONTROL2 bit register .......................................................................................... 67
• Added note to description of bits D[18:17] in CONTROL2 register .................................................................................... 67
• Changed RESERVED1 and RESERVED2 registers .......................................................................................................... 69
76 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: AFE4490