Datasheet

A7
A0 D23
D16 D15 D8 D7
D0
SPI STE
SPI SIMO
'RQ¶WFDUH, can be high or low
A7 A0
SPI CLK
D23 D16 D15 D8 D7 D0
SPI SOMI
Operation
First Write Second Write
(1, 2)
Read
(3, 4)
A7
A0 D23
D16 D15 D8 D7
D0
AFE4490
www.ti.com SBAS602F –DECEMBER 2012–REVISED OCTOBER 2013
Multiple Data Reads and Writes
The device includes functionality where multiple read and write operations can be performed during a single SPISTE event. To enable this functionality,
the first eight bits determine the register address to be written and the remaining 24 bits determine the register data. Perform two writes with the SPI read
bit enabled during the second write operation in order to prepare for the read operation, as described in the Writing Data section. In the next command,
specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the
specified register on the SPISOMI pin. This functionality is described in the Writing Data and Reading Data sections. Figure 80 shows a timing diagram
for the SPI multiple read and write operations.
(1) The SPI read register bit must be enabled before attempting a serial readout from the AFE.
(2) The second write operation must be configured for register 0 with data 000001h.
(3) Specify the register address whose contents must be read back on A[7:0].
(4) The AFE outputs the contents of the specified register on the SOMI pin.
Figure 80. Serial Multiple Read and Write Operations
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