Datasheet

RX_ANA_SUP
I/O
Pins
Device
1.8 V
1.8 V
RX_DIG_SUP
RX_ANA_SUP to
1.8-V Regulator
Rx Analog Modules
RX_DIG_SUP to
1.8-V Regulator
Rx Digital
Rx I/O
Block
AFE4490
www.ti.com SBAS602F –DECEMBER 2012–REVISED OCTOBER 2013
In ADC bypass mode, the ADC reset signal can be used to start conversions with the external ADC. Use
registers 15h through 1Ch to position the ADC reset signal edges appropriately. Also, use the CLKALMPIN[2:0]
bits on the PD_ALM pin register bit to bring out the ADC reset signal to the PD_ALM pin. ADC_RDY can be used
to indicate the start of the pulse repetition period to the external ADC.
RECEIVER SUBSYSTEM POWER PATH
The block diagram in Figure 70 shows the AFE4490 Rx subsystem power routing.
Figure 70. Receive Subsystem Power Routing
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