Datasheet
Clocking
Internal
ûADC
+
TIA
RXOUTP
+
Stage 2
Gain
RXOUTN
INP
INN
Device
External
ûADC
PD_ALM
ADC_RDY
Use the ADC_Reset
signal on the PD_ALM pin
to clock the external ADC.
Use ADC_RDY to
sync the external
ADC with the AFE.
ûADC
+
TIA
RXOUTP
+
Stage 2
Gain
RXOUTN
INP
INN
Device
AFE4490
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SBAS602F –DECEMBER 2012–REVISED OCTOBER 2013
AFE ANALOG OUTPUT MODE (ADC Bypass Mode)
This mode is only intended for use in system debug. Note that this function is not recommended for production
use because of the minimal device production testing performed on this function.
The ADC bypass mode brings out the analog output voltage of the receiver front-end on two pins (RXOUTP,
RXOUTN), around a common-mode voltage of approximately 0.9 V. In this mode, the internal ADC of the
AFE4490 is disabled. Figure 67 shows a block diagram of this mode.
Figure 67. AFE4490 Set to ADC Bypass Mode
In ADC bypass mode, one of the internal clocks (ADC_Reset) can be brought out on the PD_ALM pin, as shown
in Figure 68. This signal can be used to convert each of the four phases (within every pulse repetition period).
Additionally, the ADC_RDY signal can be used to synchronize the external ADC with the AFE. See Figure 69 for
the timing of this mode.
Figure 68. AFE4490 in ADC Bypass Mode with ADC_Reset to PD_ALM Pin
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