Datasheet

ADC Clock
ADC Convert
LED2 Data
ADC Output Rate
PRF Samples per Second
ADC
Ambient
(LED2) Data
LED1 Data
Ambient
(LED1) Data
Rx Digital
Averager
22-Bits
Register
42
LED2 Data
Register
43
LED2_Ambient Data
Register
44
LED1 Data
Register
45
LED1_Ambient Data
ADC Reset
ADC Reset
ADC
AFE4490
SBAS602F –DECEMBER 2012–REVISED OCTOBER 2013 www.ti.com
ADC OPERATION AND AVERAGING MODULE
The ADC reset signal must be positioned at 25% intervals of the pulse repetition period (that is, 0%, 25%, 50%,
and 75%). After the falling edge of the ADC reset signal, the ADC conversion phase starts (refer to Figure 63).
Each ADC conversion takes 50 µs.
There are two modes of operation: without averaging and with averaging. The averaging mode can average
multiple ADC samples and reduce noise to improve dynamic range because the ADC conversion time is usually
shorter than 25% of the pulse repetition period. Figure 64 shows a diagram of the averaging module. The ADC
output format is in 22-bit twos complement. The two MSB bits of the 24-bit data can be ignored.
Figure 64. Averaging Module
Operation Without Averaging
In this mode, the ADC outputs a digital sample one time for every 50 µs. At the next rising edge of the ADC reset
signal, the first 22-bit conversion value is written into the result registers sequentially as follows (see Figure 65):
• At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah.
• At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh.
• At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch.
• At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers
2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register
2Fh.
At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.
Operation With Averaging
In this mode, all ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge of
the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see
Figure 66):
• At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.
• At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.
• At the 75% reset signal, the averaged 22-bit word is written to register 2Ch.
• At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah
and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.
At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.
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