Datasheet

A7 A6 A1 A0
SPI STE
SPI SIMO
SCLK
t
STECLK
t
SIMOSU
t
SIMOHD
31 0
D23 D22 D1 D0
23
AFE4490
SBAS602F –DECEMBER 2012–REVISED OCTOBER 2013 www.ti.com
PARAMETRIC MEASUREMENT INFORMATION (continued)
Figure 2. Serial Interface Timing Diagram, Write Operation
Table 1. Timing Requirements for Figure 1 and Figure 2
PARAMETER MIN TYP MAX UNIT
t
CLK
Clock frequency on XIN pin 8 MHz
t
SCLK
Serial shift clock period 62.5 ns
t
STECLK
STE low to SCLK rising edge, setup time 10 ns
t
CLKSTEH,L
SCLK transition to SPI STE high or low 10 ns
t
SIMOSU
SIMO data to SCLK rising edge, setup time 10 ns
t
SIMOHD
Valid SIMO data after SCLK rising edge, hold time 10 ns
t
SOMIPD
SCLK falling edge to valid SOMI, setup time 17 ns
t
SOMIHD
SCLK rising edge to invalid data, hold time 0.5 t
SCLK
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