Datasheet

AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012 www.ti.com
Table 10. Gain Select Register: Address 0x02
Default: 0x32
Gain Select Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
This bit is used to set the gain of the Rx PGA1.
00 = 0.25 V/V
RX1G-0,
0, 1 0, 1 R/W 01 = 0.5 V/V
RX1G-1
10 = 1 V/V
11 = 2 V/V
This bit is used to set the gain of the Rx PGA2.
00 = 1 V/V
RX2G-0,
2, 3 0, 0 R/W 01 = 4 V/V
RX2G-1
10 = 16 V/V
11 = 64 V/V
This bit is used to set the gain of the Tx PGA.
00 = 0.25 V/V
TXG-0,
4, 5 1, 1 R/W 01 = 0.5 V/V
TXG-1
10 = 0.707 V/V
11 = 1 V/V
-- 6 0 -- Reserved
-- 7 0 -- Reserved
Table 11. Enable2 Register: Address 0x03
Default: 0x00
Enable2 Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
This bit is used to enable/disable the ZC Block.
ZC 0 0 R/W
0 = disabled, 1 = enabled.
This bit is used to enable/disable the REF1 Block.
REF1 1 0 R/W
0 = disabled, 1 = enabled.
This bit is used to enable/disable the REF2 Block.
REF2 2 0 R/W
0 = disabled, 1 = enabled.
This bit is used to enable/disable the PA output stage.
When the PA output stage is enabled it functions normally with a
low output impedance, capable of driving heavy loads.
PA_OUT 3 0 R/W
When the PA output stage is disabled it is placed into a high
impedance state.
0 = disabled, 1 = enabled.
-- 4 0 -- Reserved
-- 5 0 -- Reserved
-- 6 0 -- Reserved
-- 7 0 -- Reserved
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