Datasheet
Table Of Contents
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- ELECTRICAL CHARACTERISTICS: Transmitter (Tx)
- ELECTRICAL CHARACTERISTICS: Power Amplifier (PA)
- ELECTRICAL CHARACTERISTICS: Receiver (Rx)
- ELECTRICAL CHARACTERISTICS: Digital
- ELECTRICAL CHARACTERISTICS: Two-Wire Interface
- ELECTRICAL CHARACTERISTICS: Internal Bias Generator
- ELECTRICAL CHARACTERISTICS: Power Supply
- THERMAL INFORMATION
- SPI TIMING REQUIREMENTS
- DEVICE INFORMATION
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- Revision History
AFE031
www.ti.com
SBOS531D –AUGUST 2010–REVISED MAY 2012
SERIAL INTERFACE
The AFE031 is controlled through a serial interface that allows read/write access to the control and data
registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted
out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid
host SPI communications protocol. Table 7 through Table 16 show the complete register information.
Table 7. Data Register
REGISTER ADDRESS DEFAULT FUNCTION
ENABLE1 0x01 0x00 Block enable or disable
GAIN SELECT 0x02 0x32 Rx and Tx gain select
ENABLE2 0x03 0x00 Block enable or disable
CONTROL1 0x04 0x00 Frequency select and calibration, Tx and Rx status
CONTROL2 0x05 0x01 Interrupt enable
RESET 0x09 0x00 Interrupt status and device reset
DIE_ID 0x0A 0x00 Die name
REVISION 0x0B 0x02 Die revision
Table 8. Command Register
LOCATION
BIT NAME (15 = MSB) R/W FUNCTION
ADDR8 8 W Register address bit
ADDR9 9 W Register address bit
ADDR10 10 W Register address bit
ADDR11 11 W Register address bit
ADDR12 12 W Register address bit
ADDR13 13 W Register address bit
ADDR14 14 W Register address bit
R/W 15 W Read/write: read = 1, write = 0
Table 9. Enable1 Register: Address 0x01
Default: 0x00
Enable1 Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
This bit is used to enable/disable the PA Block.
PA 0 0 R/W
0 = disabled, 1 = enabled.
This bit is used to enable/disable the Tx Block.
TX 1 0 R/W
0 = disabled, 1 = enabled.
This bit is used to enable/disable the Rx Block.
RX 2 0 R/W
0 = disabled, 1 = enabled.
This bit is used to enable/disable the ERx Block.
ERX 3 0 R/W
0 = disabled, 1 = enabled.
This bit is used to enable/disable the ETx Block.
ETX 4 0 R/W
0 = disabled, 1 = enabled.
This bit is used to enable/disable the DAC Block.
DAC 5 0 R/W 0 = DAC disabled; switch is connected to Tx_PGA_IN pin.
1 = DAC enabled; switch is connected to DAC output.
-- 6 0 -- Reserved
-- 7 0 -- Reserved
Copyright © 2010–2012, Texas Instruments Incorporated 35
Product Folder Link(s): AFE031