Datasheet

CS
SCLK
DIN
DOUT
t
CSSC
t
SU
t
HD
t
LO
t
HI
t
DO
t
SOZ
t
CS1
t
CS0
t
SCCS
t
CSH
1/f
SCLK
Hi-Z
Hi-Z
AFE031
www.ti.com SBOS531D –AUGUST 2010–REVISED MAY 2012
SPI TIMING REQUIREMENTS
PARAMETER CONDITION MIN TYP MAX UNIT
Input capacitance 1 pF
Input rise/fall time t
RFI
CS, DIN, SCLK 2 ns
Output rise/fall time t
RFO
DOUT 10 ns
CS high time t
CSH
CS 20 ns
SCLK edge to CS fall setup time t
CS0
10 ns
CS fall to first SCLK edge setup time t
CSSC
10 ns
SCLK frequency f
SCLK
20 MHz
SCLK high time t
HI
20 ns
SCLK low time t
LO
20 ns
SCLK last edge to CS rise setup time t
SCCS
10 ns
CS rise to SCLK edge setup time t
CS1
10 ns
DIN setup time t
SU
10 ns
DIN hold time t
HD
5 ns
SCLK to DOUT valid propagation delay t
DO
20 ns
CS rise to DOUT forced to Hi-Z t
soz
20 ns
TIMING DIAGRAMS
Figure 1. SPI Mode 0,0
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Product Folder Link(s): AFE031