Datasheet

AFE030
SBOS588A DECEMBER 2011 REVISED DECEMBER 2011
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SERIAL INTERFACE
The AFE030 is controlled through a serial interface that allows read/write access to the control and data
registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted
out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid
host SPI communications protocol. Table 7 through Table 16 show the complete register information.
Table 7. Data Register
REGISTER ADDRESS DEFAULT FUNCTION
ENABLE1 01h 00h Block enable or disable
GAIN SELECT 02h 32h Rx and Tx gain select
ENABLE2 03h 00h Block enable or disable
CONTROL1 04h 00h Frequency select and calibration, Tx and Rx status
CONTROL2 05h 01h Interrupt enable
RESET 09h 00h Interrupt status and device reset
DIE_ID 0Ah 01h Die name
REVISION 0Bh 02h Die revision
Table 8. Command Register
LOCATION
BIT NAME (15 = MSB) R/W FUNCTION
ADDR8 8 W Register address bit
ADDR9 9 W Register address bit
ADDR10 10 W Register address bit
ADDR11 11 W Register address bit
ADDR12 12 W Register address bit
ADDR13 13 W Register address bit
ADDR14 14 W Register address bit
R/W 15 W Read/write: read = 1, write = 0
Table 9. Enable1 Register: Address 00h
Default: 00h
Enable1 Register <7:0>
LOCATION
BIT NAME (0 = LSB) DEFAULT R/W FUNCTION
This bit is used to enable/disable the PA block.
PA 0 0 R/W 0 = Disabled
1 = Enabled
This bit is used to enable/disable the Tx block.
TX 1 0 R/W 0 = Disabled
1 = Enabled
This bit is used to enable/disable the Rx block.
RX 2 0 R/W 0 = Disabled
1 = Enabled
This bit is used to enable/disable the ERx block.
ERX 3 0 R/W 0 = Disabled
1 = Enabled
This bit is used to enable/disable the ETx block.
ETX 4 0 R/W 0 = Disabled
1 = Enabled
This bit is used to enable/disable the DAC block.
DAC 5 0 R/W 0 = DAC disabled; switch is connected to Tx_PGA_IN pin.
1 = DAC enabled; switch is connected to DAC output.
6 0 Reserved
7 0 Reserved
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