Datasheet

C =
IN
(2 f )p
HP
´ ´ ´20 kW
1
R = 20 k
SET
´
- 15 kW
1.2 V
I
LIM
( (
AFE030
www.ti.com SBOS588A –DECEMBER 2011– REVISED DECEMBER 2011
The external capacitor, C
IN
, introduces a single-pole, high-pass characteristic to the PA transfer function;
combined with the inherent low-pass transfer function, this characteristic results in a passband response. The
value of the high-pass cutoff frequency is determined by C
IN
reacting with the input resistance of the PA circuit,
and can be found from Equation 1:
(1)
Where:
• C
IN
= external input capacitor
• f
HP
= desired high-pass cutoff frequency
For example, setting C
IN
to 3.3 nF results in a high-pass cutoff frequency of 2.4 kHz. The voltage rating for C
IN
should be determined to withstand operation up to the PA power-supply voltage.
When the transmitter is not in use, the output can be disabled and placed into a high-impedance state by writing
a '0' to the PA-OUT bit in the Enable2 Register. Additional power savings can be realized by shutting down the
PA when not in use. Shutting down the PA for power savings is accomplished by writing a '0' to the PA bit in the
Enable1 Register. Shutting down the PA also results in the PA output entering a high-impedance state. When the
PA shuts down, it consumes only 2 mW of power.
The PA_ISET pin (pin 46) provides a resistor-programmable output current limit for the PA block. Equation 2
determines the value of the external R
SET
resistor attached to this pin.
(2)
Where:
• R
SET
= the value of the external resistor connected between pin 46 and ground.
• I
LIM
= the value of the desired current limit for the PA.
Note that to ensure proper design margin with respect to manufacturing and temperature variations, a 30%
increase in the value used in Equation 2 for I
LIM
over the nominal value of I
LIM
is recommended. See Figure 20,
PA Current Limit vs R
SET
. For maximum output current, PA_ISET (pin 46) may be connected directly to ground.
Tx Block
The Tx block consists of the Tx PGA and Tx Filter. The Tx PGA is a low-noise, high-performance, programmable
gain amplifier. In DAC mode (where pin 7 is a logical '1' and Enable1 Register bit location 5 is a logical '1'), the
Tx PGA operates as the internal digital-to-analog converter (DAC) output buffer with programmable gain. In
PWM mode (where pin 7 is a logical '0' and Enable1 Register bit location 5 is a logical '0'), the Tx PGA operates
as a stand-alone programmable gain amplifier. The Tx PGA gain is programmed through the serial interface. The
Tx PGA gain settings are 0.25 V/V, 0.5 V/V, 0.707 V/V, and 1 V/V.
The Tx Filter is a unity-gain, fourth-order low-pass filter. The Tx Filter cutoff frequency is selectable between
CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD)
determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band;
setting Control1 Register bit location 3 to '1' selects CENELEC B, C, and D bands.
The AFE030 supports both DAC inputs or PWM inputs for the Tx signal path. DAC mode is recommended for
best performance. In DAC mode, no external components in the Tx signal path are required to meet regulatory
signal emissions requirements. When in DAC mode, the AFE030 accepts serial data from the microprocessor
and writes that data to the internal DAC registers. When in DAC mode (where pin 7 is a logical '1' and Enable1
Register bit location 5 is a logical '1'), the Tx PGA output must be directly coupled to the Tx_FIN1 input and the
unused Tx_FIN2 input must be grounded.
Copyright © 2011, Texas Instruments Incorporated 23
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