Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 10 Bit VQFN 48

DVDD

DGND

AGND1

AVDD1

AGND2

AVDD2

SCLK

DAC

Tx_FLAG

Rx_FLAG

INT

REF1

REF2

ZC_OUT2

ZC_OUT1

ZC_IN1

ZC_IN2

PA_ISET

PA_VS

PA_GND

TSENSE

PA_OUT

E_Rx_IN

E_Rx_OUT

E_Tx_CLK

E_Tx_IN

E_Tx_OUT

Rx_PGA1_IN

Rx_PGA1_OUT

Rx_F_IN

Rx_C1

Rx_C2

Rx_F_OUT

Tx_PGA_IN

TX_PGA_OUT

Tx_F_IN1

Tx_F_IN2

Tx_F_OUT

PA_IN

Rx_PGA2_OUT

Rx_PGA2_IN

Bias

ZC2

ZC1

Power

Amplifier

Digital Interface

(SPI)

Control

Digital-to-Analog

Converter

TxPGA

RxPGA_1

RxPGA_2

Tx Filter

Rx Filter

Two-Wire Rx/Tx

Device

AFE030

www.ti.com

SBOS588A –DECEMBER 2011– REVISED DECEMBER 2011

Powerline Communications Analog Front-End

Check for Samples: AFE030

FEATURES

DESCRIPTION

The AFE030 is a low-cost, integrated, powerline

234

• Integrated Powerline Driver with Thermal and

communications (PLC) analog front-end (AFE) device

Overcurrent Protection

that is capable of capacitive- or transformer-coupled

• Conforms to EN50065-1

connections to the powerline while under the control

• Pin-Compatible to AFE031

of a digital signal processor (DSP) or microcontroller.

It is ideal for driving low-impedance lines that require

• Large Output Swing: 13 V

at 1.0 A

up to 1.0 A into reactive loads. The integrated

(15-V Supply)

receiver is able to detect signals down to 20 μV

RMS

• Low Power Consumption: 15 mW

and is capable of a wide range of gain options to

(Receive Mode)

adapt to varying input signal conditions. This

monolithic integrated circuit provides high reliability in

• Programmable Tx and Rx Filters

demanding powerline communications applications.

• Supports EN50065 CENELEC Bands A, B, C, D

The AFE030 transmit power amplifier operates from a

• Supports OFDM, FSK, and S-FSK

single supply in the range of 7 V to 26 V. At

• Supports IEC 61334

maximum output current, a wide output swing

• Receive Sensitivity: 20 μV

RMS

, Typical

provides a 12-V

OUT

= 1.0 A) capability with a

nominal 15-V supply. The analog and digital signal

• Programmable Tx/Rx Gain Control

processing circuitry operates from a single 3.3-V

• Four-Wire Serial Peripheral Interface

power supply.

• Two Integrated Zero Crossing Detectors

The AFE030 is internally protected against

• Two-Wire Transceiver Buffer

overtemperature and short-circuit conditions. It also

• Package: QFN-48 PowerPAD™

provides an adjustable current limit. An interrupt

output is provided that indicates both current limit and

• Extended Junction Temperature Range:

thermal limit. There is also a shutdown pin that can

–40°C to +125°C

be used to quickly put the device into its lowest

power state. Through the four-wire serial peripheral

APPLICATIONS

interface, or SPI™, each functional block can be

• eMetering

enabled or disabled to optimize power dissipation.

• Lighting

The AFE030 is housed in a thermally-enhanced,

• Solar

surface-mount PowerPAD package (QFN-48).

Operation is specified over the extended industrial

• Pilot Wire

junction temperature range of –40°C to +125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD, C2000 are trademarks of Texas Instruments.

3SPI is a trademark of Motorola, Inc.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (58 pages)

PAGE 1
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Powerline Communications Analog Front-End Check for Samples: AFE030 FEATURES DESCRIPTION • Integrated Powerline Driver with Thermal and Overcurrent Protection • Conforms to EN50065-1 • Pin-Compatible to AFE031 • Large Output Swing: 13 VPP at 1.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Transmitter (Tx), Tx_DAC At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER CONDITIONS Output range Resolution THD Total harmonic distortion at 62.5 kHz (1) MIN MAX AVDD – 0.1 UNIT V 1024 steps, 10-bit DAC 3.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Transmitter (Tx), Tx_FILTER At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER CONDITIONS MIN TYP MAX UNIT INPUT GND – 0.1 Input voltage range RI Input resistance (Tx_F_IN1 and Tx_F_IN2) AVDD + 0.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Power Amplifier (PA) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER CONDITIONS MIN TYP MAX UNIT INPUT GND – 0.1 Input voltage range RI Input resistance PA_VS + 0.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Receiver (Rx), Rx PGA1 At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER CONDITIONS MIN TYP MAX UNIT INPUT Input voltage range RI Input resistance 10 VPP G = 2 V/V 10 kΩ G = 1 V/V 15 kΩ G = 0.5 V/V 20 kΩ G = 0.25 V/V 24 kΩ G = 2 V/V 6 MHz G = 1 V/V 10 MHz G = 0.5 V/V 13 MHz G = 0.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Receiver (Rx), Rx Filter At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER CONDITIONS MIN TYP MAX UNIT INPUT GND – 0.1 Input voltage range RIN Input resistance AVDD + 0.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Receiver (Rx), Rx PGA2 At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER CONDITIONS MIN TYP MAX UNIT INPUT GND – 0.1 Input voltage range RI Input impedance AVDD + 0.1 V G = 64 V/V 1.7 kΩ G = 16 V/V 6.3 kΩ G = 4 V/V 21 kΩ G = 1 V/V 53 kΩ G = 64 V/V 300 kHz G = 16 V/V 800 kHz G = 4 V/V 1.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Digital At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER CONDITIONS MIN TYP MAX –1 0.01 1 UNIT DIGITAL INPUTS (SCLK, DIN, CS, DAC, SD) Leakage input current VIH High-level input voltage VIL Low-level input voltage 0 ≤ VIN ≤ DVDD 0.7 × DVDD μA V 0.3 × DVDD SD pin high SD > 0.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Two-Wire Interface At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. AFE030 PARAMETER CONDITIONS MIN TYP MAX UNIT TWO-WIRE TRANSMITTER Frequency range (1) Leakage input current (E_Tx_In, E_Tx_Clk) 50 0 ≤ VIN ≤ DVDD –1 0.01 kHz 1 μA INPUT LOGIC LEVELS (E_Tx_In, E_Tx_Clk) VIH High-level input voltage VIL Low-level input voltage 0.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS: Internal Bias Generator At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com THERMAL INFORMATION AFE030 THERMAL METRIC (1) RGZ (QFN) UNITS 48 PINS θJA Junction-to-ambient thermal resistance 27.8 θJCtop Junction-to-case (top) thermal resistance 12.1 θJB Junction-to-board thermal resistance 7.5 ψJT Junction-to-top characterization parameter 0.4 ψJB Junction-to-board characterization parameter 7.4 θJCbot Junction-to-case (bottom) thermal resistance 1.
PAGE 13
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TIMING DIAGRAMS tCSH CS tCSSC tSCCS tLO tCS1 tCS0 tHI SCLK tSU 1/fSCLK tHD DIN tSOZ tDO Hi-Z Hi-Z DOUT Figure 1. SPI Mode 0,0 tCSH CS tCSSC tSCCS tHI tCS1 tCS0 tLO SCLK tSU tHD 1/fSCLK DIN tSOZ tDO Hi-Z Hi-Z DOUT Figure 2. SPI Mode 1,1 CS SDI SDO W0 XX W1 XX W2 XX W3 XX W - Command of Write Register N XX - Don’t care; undefined. Figure 3.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com CS SDI SDO R0 R1 D0 XX Any Command R3 R2 D1 D3 D2 R - Command of Read Register N Read D - Data from Register N XX - Don’t care; undefined. Figure 4.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com PIN DESCRIPTIONS AFE030 PIN NO.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. Tx Filter GAIN vs FREQUENCY Rx Filter GAIN vs FREQUENCY 20 20 CENELEC A CENELEC B,C,D 0 0 −10 −10 −20 −30 −20 −30 −40 −40 −50 −50 −60 10k 100k Frequency (Hz) CENELEC A CENELEC B,C,D 10 Gain (dB) Gain (dB) 10 −60 10k 1M 100k Frequency (Hz) G001 Figure 5.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted.
PAGE 19
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. Rx PGA2 GAIN ERROR vs TEMPERATURE QUIESCENT SUPPLY CURRENT vs TEMPERATURE 0.4 60 0.3 Supply Current (mA) 0.2 Gain Error (%) PA Current (PA Enabled) AVDD Current (RX Mode) AVDD Current (TX Mode) 50 0.1 0 −0.1 −0.2 40 30 20 10 −0.3 −0.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and PA_ISET (pin 46) connected to ground, unless otherwise noted. Rx PULSE RESPONSE 0.2 Rx Filter CENELEC A Rx Filter CENELEC B 0.15 Voltage (V) 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 0 10 µs/div (dB) G019 Figure 23.
PAGE 21
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com APPLICATION INFORMATION GENERAL DESCRIPTION The AFE030 is an integrated powerline communication analog front-end (AFE) device built from a variety of functional blocks that work in conjunction with a microcontroller. The AFE030 provides the interface between the microcontroller and a line coupling circuit. The AFE030 delivers high performance and is designed to work with a minimum number of external components.
PAGE 22
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com BLOCK DESCRIPTIONS PA Block The Power Amplifier (PA) block consists of a high slew rate, high-voltage, and high-current operational amplifier. The PA is configured with an inverting gain of 6.5 V/V, has a low-pass filter response, and maintains excellent linearity and low distortion. The PA is specified to operate from 7 V to 26 V and can deliver up to ±1.
PAGE 23
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com The external capacitor, CIN, introduces a single-pole, high-pass characteristic to the PA transfer function; combined with the inherent low-pass transfer function, this characteristic results in a passband response.
PAGE 24
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com The proper connections for the Tx signal path for DAC mode operation are shown in Figure 27. Operating in DAC mode results in the lowest distortion signal injected onto the ac mains. No additional external filtering components are required to meet CENELEC requirements for A, B, C or D bands when operating in DAC mode.
PAGE 25
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com See Note 1 Inside the AFE030 MCU 43 kW Tx_F_IN1 PA_OUT1 GPIO PGA LPF Tx_F_IN2 PA GPIO PA_OUT2 43 kW Tx_F_OUT Tx_PGA_ Tx_PGA_ IN OUT PA_IN C C= 1 See Note 2 2 ´ p ´ f ´ 22 kW (1) When using both Tx Filter inputs, use 43-kΩ resistors to match the input resistance for best frequency response. (2) For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance. Figure 29.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com See Note 1 Inside the AFE030 MCU 43 kW Tx_F_IN1 PA_OUT1 GPIO Tx_F_IN2 PGA LPF PA GPIO PA_OUT2 43 kW Tx_F_OUT 510 W Tx_PGA_ Tx_PGA_ IN OUT PA_IN 510 W C C C C= 1 See Note 3 2 ´ p ´ f ´ 22 kW See Note 2 (1) When using both Tx Filter inputs, use 43-kΩ resistors to match the input resistance for best frequency response. (2) Refer to Table 2.
PAGE 27
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com The Rx Filter is a very low noise, unity-gain, fourth-order low-pass filter. The Rx Filter cutoff frequency is selectable between CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD) determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band; setting Control1 Register bit location 3 to '1' selects the CENELEC B, C, and D bands.
PAGE 28
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com The following steps can be used to quickly design the passive passband filter. (Note that these steps produce an approximate result.) 1. Choose the filter characteristic impedance, ZC: – For –6-db passband attenuation: R1 = R2 = ZC – For 0-db passband attenuation: R1 = ZC, R2 = 10 × ZC 2.
PAGE 29
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com The Rx PGA1, Rx Filter, and Rx PGA2 components have all inputs and outputs externally available to provide maximum system design flexibility. Care should be taken when laying out the PCB traces from the inputs or outputs to avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or outputs to ground, below 100 pF is recommended.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Refer to Figure 35 for an illustration of this sequence. CS DAC DIN SCLK Time Figure 35. Writing to the DAC Register Table 6 lists the DAC Register configurations. Table 6.
PAGE 31
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com REF1 and REF2 Blocks The REF1 and REF2 blocks create midscale power-supply biasing points used internally to the AFE030. Each reference divides its respective power-supply voltage in half with a precision resistive voltage divider. REF1 provides a PA_VS/2 voltage at the output of the PA, while REF2 provides an AVDD/2 voltage at the outputs of the Tx PGA, Tx Filter, Rx PGA1, Rx Filter, and Rx PGA2.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Zero Crossing Detector Block The AFE030 includes two zero crossing detectors. Zero crossing detectors can be used to synchronize communications signals to the ac line or sources of noise. Typically, in single-phase applications, only a single zero crossing detector is used. In three-phase applications, both zero crossing detectors can be used; one component detects phase A, and one detects phase B.
PAGE 33
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com For maximum protection of the AFE030 against line transients, it is recommended to use Schottky diodes as indicated in Figure 38. These diodes should limit the ZC_IN pins (pins 38 and 39) to within the maximum rating of (AVDD + 0.4 V) and (AGND – 0.4 V). Some applications may require an isolated zero crossing detection circuit.
PAGE 34
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com ETx and ERx Blocks The AFE030 contains a two-wire transmitter block, ETx, and a two-wire receiver block, ERx. These blocks support communications that use amplitude shift keying (ASK) with on-off keying (OOK) modulation. The ETx block is a gated driver that allows for transmission of a carrier input signal and modulating input signal.
PAGE 35
AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com The E_Rx_Out pin can be directly connected to either an available analog-to-digital converter (ADC) input or GPIO on the host microcontroller. Figure 44 illustrates a typical two-wire application for ETx and ERx. Device Internal Configuration E_Tx_In TMS320F28x E_Tx_Out GPIO Flexible PLC Software Engine CEXT E_Rx_In E_Tx_CLK GPIO + N1 + N2 Two-Wire Bus E_Rx_Out GND GPIO Figure 44.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com SERIAL INTERFACE The AFE030 is controlled through a serial interface that allows read/write access to the control and data registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid host SPI communications protocol.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Table 10. Gain Select Register: Address 02h Default: 32h Gain Select Register <7:0> BIT NAME RX1G-0, RX1G-1 RX2G-0, RX2G-1 TXG-0, TXG-1 LOCATION (0 = LSB) 0, 1 2, 3 DEFAULT 0, 1 0, 0 R/W FUNCTION R/W This bit is used to set the gain of the Rx PGA1. 00 = 0.25 V/V 01 = 0.5 V/V 10 = 1 V/V 11 = 2 V/V R/W This bit is used to set the gain of the Rx PGA2.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Table 12. Control1 Register: Address 04h Default: 00h Control1 Register <7:0> BIT NAME LOCATION (0 = LSB) DEFAULT R/W FUNCTION TX_CAL 0 0 R/W This bit is used to enable/disable the TX calibration mode. 0 = Disabled 1 = Enabled RX_CAL 1 0 R/W This bit is used to enable/disable the RX calibration mode. 0 = Disabled 1 = Enabled TX_PGA_CAL 2 0 R/W This bit is used to enable/disable the TX PGA calibration mode.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Table 14. RESET Register: Address 09h Default: 00h Reset Register <7:0> BIT NAME LOCATION (0 = LSB) DEFAULT R/W -- 0 0 -- Reserved -- 1 0 -- Reserved 2, 3, 4 0, 0, 0 W These bits are used to perform a software reset of the ENABLE1, ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT registers. Writing '101' to these registers performs a software reset. R/W This bit is used to indicate the status of a PA thermal overload.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com POWER SUPPLIES The AFE030 has two low-voltage analog power-supply pins and one low-voltage digital supply pin. Internally, the two analog supply pins are connected to each other through back-to-back electrostatic discharge (ESD) protection diodes. These pins must be connected to each other on the application printed circuit board (PCB).
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com PIN DESCRIPTIONS DAC (Pin 7) The DAC pin is used to configure the SPI to either read or write data to the Command and Data Registers, or to write data to the DAC registers. Setting the DAC pin high allows access to the DAC registers. Setting the DAC pin low allows access to the Command and Data Registers. SD (Pin 8) The Shutdown pin (SD) can be used to shut down the entire AFE030 for maximum power savings.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Table 18 lists the register contents associated with each interrupt condition. Table 18.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com CALIBRATION MODES The AFE030 can be configured for three different calibration modes: Tx Calibration, Rx Calibration, and Tx PGA Calibration. Calibration values can be determined during the calibration process and stored in system memory.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Tx PGA Calibration Mode The Tx PGA ac gain can be calibrated in Tx PGA Calibration mode. Figure 48 shows the signal path during Tx PGA Calibration mode. C2000 MCU Device Line-Coupling Interface DAC PGA PA LPF SPI SPI PGA PGA LPF Figure 48. Tx PGA Calibration Mode Configuration BASIC CONFIGURATION Figure 49 shows the AFE030 configured in a typical PLC analog front-end application.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com +15 V C5 C13 C15 C14 10 mF 10 mF 3.3 V C16 10 mF 10 mF D1 100 nF C6 10 mF D2 R1 R2 33 kW 1.5:1 Coilcraft DA2302-AL 33 kW D3 GPIO + N1 R12 4.7 W 38 L2 15 mH Phase + N2 Neutral D4 TVS C17 10 nF 37 40 39 41 43 42 44 46 3.3 V 45 R6 through R9 48 3.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com LINE-COUPLING CIRCUIT The line-coupling circuit is one of the most critical circuits in a powerline modem. The line-coupling circuit has two primary functions: first, to block the low-frequency signal of the mains (commonly 50 Hz or 60 Hz) from damaging the low-voltage modem circuitry; second, to couple the modem signal to and from the ac mains. A typical line-coupling circuit is shown in Figure 50.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Table 19 lists several recommended transient protection components. Table 19. Recommended Transient Protection Devices 120 VAC, 60 Hz COMPONENT DESCRIPTION MANUFACTURER MFR PART NO (OR EQUIVALENT) D1 Zener diode Diodes, Inc. 1SMB59xxB (1) D2, D3 Schottky diode Diodes, Inc.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Some heat is conducted from the silicon die surface through the plastic packaging material and is transferred into the ambient environment. Because plastic is a relatively poor conductor of heat, however, this route is not the primary thermal path for heat flow. Heat also flows across the silicon die surface to the bond pads, through the wire bonds, into the package leads, and finally into the top layer of the PCB.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com Increasing the number of layers in the PCB, using thicker copper, and increasing the PCB area are all factors that improve the spread of heat. Figure 55 through Figure 57, respectively, show thermal resistance performance as a function of each of these factors.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com For additional information on thermal PCB design using exposed thermal pad packages, refer to Application Report SBOA130, Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the AFE031 and Application Report SLMA002E, PowerPAD™ Thermally-Enhanced Package (both available for download at www.ti.com). Powerline Communications Developer’s Kit A PLC developer’s kit (TMDSPLCKIT-V3) is available to order at www.ti.
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AFE030 SBOS588A – DECEMBER 2011 – REVISED DECEMBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (December 2011) to Revision A Page • Changed product status to Production Data .........................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant AFE030AIRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 AFE030AIRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE030AIRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 AFE030AIRGZT VQFN RGZ 48 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.