Datasheet

DATA READ
IRST
SHR
INTG
SHS
STI
CLK
TFT ON (t5)
~0.5 uSec
t1
t1
t1
t2
t3
t4
t6
t7
t8
t- Scan
EOC
t9
1 2 33 65 132 133
1 2 8 17 32 33
IRST
CLK
SHR
LPF o
n
Internal Reset End
TFT turned on
Reset Sample
Integratoro
/
pat
resetlevel
Deviceintegratinginput
channelleakagecurrent
Deviceintegratingacquired
charge
Integrator
o/p
RST sampleBW
limitedbyfilter
ClkNoinSequentialmode
ClkNoinSimultmode
32
8
64
16
AFE0064
www.ti.com ........................................................................................................................................................................................ SLAS672 –SEPTEMBER 2009
Figure 2. Integration and Data Read
As shown in Figure 2, the device performs two functions, ‘Integration’ and ‘Data Read’ during each scan
(indicated by 't-Scan'). Signals IRST, SHR, SHS, INTG, CLK control 'Integration Function' and STI, CLK control
'Data Read Function'. EOC is a device output and a low level on the EOC pin indicates a data read is in
progress.
Charge Integration
Integration function consists of two phases namely ‘Reset’ and ‘Integration’.
IRST rising edge starts the ‘Reset’ phase which ends with SHR rising edge. Figure 3 shows the detailed timing
waveform for the reset phase.
Figure 3. Timing Diagram Showing Details of Reset Phase
In this phase the device resets all 64 integration capacitors. This reset-level voltage depends on the integration
mode (selected by the INTUPz pin). Integrator output is reset to REFM for ‘integration-up’ mode and is reset to
REFP in ‘integration-down’ mode. Note that the integrator reset switch is on from IRST rising edge to the end of
the 32
nd
clock for sequential mode and up to the 8th clock for simultaneous mode. SHR and filter bypass
switches (see Figure 1) are on right from IRST rising edge to the 64
th
clock falling edge.
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