Datasheet

AFE0064
www.ti.com
........................................................................................................................................................................................ SLAS672 SEPTEMBER 2009
PIN FUNCTIONS (continued)
PIN
I/O DESCRIPTION
NUMBER NAME
78 OUTP-1 O Driver 1-analog output positive terminal
77 OUTM-1 O Driver 1-analog output negative terminal
Driver 1 outputs analog data for channels 63 to 32
Note that the device output is differential (OUTP-OUTM) with common mode of (OUTP+OUTM)/2
REFERENCE
105 REFP I Positive reference input
104 REFM I Negative reference input
Decouple REFP and REFM terminals to VSS with suitable capacitor and use low noise reference, noise on these terminals will add to noise
at output terminals.
112 EXT_C O Terminal available for decoupling internally generated integrator common-mode voltage (1.68 V).
Decouple this pin to VSS with 1 µF ceramic capacitor.
Internally connected to +ve terminals of all 64 integrators.
50 P_REF O Internally generated 1.68 V reference output available for referencing photodiode cathodes.
CONTROL PINS
63 STO O Delayed ST for cascading next ASIC
64 EOC O End of data shifting, EOC is low during data read.
66 INTG I Filter bandwidth control for Signal sample (SHS). Filter BW is high when this signal is high and
filter BW is low when this signal is low. Typically this signal should go high with TFT switch turn on
and should go low ~0.5 µSec after TFT switch off.
67 IRST I Resets the integrator capacitors on rising edge of this input.
68 SHS I Device samples 'signal' level of integrator output(0 to 63) onto the respective CDS on rising edge
of this input.
69 SHR I Device samples 'reset' level of integrator output (0 to 63) onto the respective CDS on rising edge
of this input.
70 CLK I For simultaneous mode: Device serially outputs the analog voltage from each integrator channel
on each rising edge of CLK.
For sequential mode: Device serially outputs the analog voltage from each integrator channel on
every fourth rising edge of CLK.
88 PDz I Low level puts device in powerdown mode.
89 NAPz I Low level puts device in NAP mode, this is useful for power saving during X-ray exposure period.
92 ENTRI I High on this pin enables 3-state of analog output drivers after shift out of data for all 64 channels.
97 STI I Rising edge resets the channel counter. Falling edge enables data transfer on OUTP and OUTM
terminals.
PGA-I/P RANGE SELECTION
94 PGA-2 I Selects eight different analog input ranges. Three bit word with these three bits represents binary
number corresponding to Analog Input Range. PGA-2 is MSB and PGA-0 is LSB. Example 000 is
95 PGA-1 I
range 0 and 100 is range 4.
96 PGA-0 I
MODE SELECTION
93 INTUPz I High level selects 'integration-down' mode. In this mode device integrates positive pixel current
into each channels, starting from reset level (REFP) down to REFM low level selects
'integration-up' mode. In this mode the device integrates negative pixel current into each channel,
starting from reset level (REFM) up to REFP.
98 SMT-MD I High level selects simultaneous mode. Device outputs data simultaneously on both differential
output drivers OUTP-OUTM<0> and OUTP-OUTM<1> in this mode.
Low level on this input selects sequential mode. In this mode device output data for driver 0 is
skewed by two clocks from driver 1. This is useful when a two channel multiplexed ADC is used
after AFE.
POWER SUPPLY
53, 55, 60, VDD I Device power supply
61, 75, 81,
87, 100, 106,
108
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